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Motorola DSP56301 user manual Lble

Models: DSP56301

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movep X:M_DRXR,y0 insert x1,x0,a insert y1,y0,a move a1,r0

move a0,a1

;Download P memory through UB lsr a r0,r1

do a1,_LOOP4

_LBLE

jset #2,X:M_DSR,_LBLF jclr #3,X:M_DSR,_LBLE bra <TERMINATE

_LBLF

movep X:M_DRXR,a0

_LBLG

jset #2,X:M_DSR,_LBLH jclr #3,X:M_DSR,_LBLG bra <TERMINATE

_LBLH

movep X:M_DRXR,x0

_LBLI

jset #2,X:M_DSR,_LBLJ jclr #3,X:M_DSR,_LBLI bra <TERMINATE

_LBLJ

movep X:M_DRXR,y0 insert x1,x0,a insert y1,y0,a movem a0,p:(r0)+ movem a1,p:(r0)+ nop

_LOOP4

bra <FINISH

;Store starting address

;concatenate next 16-bit word

;concatenate next 16-bit word

;start to p-mem

;number of words to transfer

;divide loop count by 2 and save r0

;Load instruction words

;Wait for SRRQ to go high (i.e. data ready)

;If HF0=1, stop loading new data.

;Terminate loop (enddo) and finish

;Store 16-bit data in accumulator

;Wait for SRRQ to go high (i.e. data ready)

;If HF0=1, stop loading new data.

;Terminate loop (enddo) and finish

;Store 16-bit data in register

;Wait for SRRQ to go high (i.e. data ready)

;If HF0=1, stop loading new data.

;Terminate loop (enddo) and finish

;Store 16-bit data in register

;concatenate next 16-bit word

;concatenate next 16-bit word

;Store 24-bit data in P mem.

;Store 24-bit data in P mem.

;movem cannot be at LA.

;and go get another 24-bit word.

;finish bootstrap

;========================================================================

;This is the routine that loads from the Host Interface in PCI mode.

;MD:MC:MB:MA=x100 - Host PCI

PCIHOSTLD

 

bset #20,X:M_DCTR

; Configure HI32 as PCI

UB3_CONT

 

jclr #2,X:M_DSR,*

; Wait for SRRQ to go high (i.e. data ready)

movep X:M_DRXR,a0

; Store number of words

jclr #2,X:M_DSR,*

; Wait for SRRQ to go high (i.e. data ready)

movep X:M_DRXR,r0

; Store starting address

move r0,r1

; save r0

do a0,_LOOP5

; Load instruction words

_LBLK

 

jset #2,X:M_DSR,_LBLL jclr #3,X:M_DSR,_LBLK bra <TERMINATE

_LBLL

movep X:M_DRXR,P:(R0)+ nop

_LOOP5

;Wait for SRRQ to go high (i.e. data ready)

;If HF0=1, stop loading data. Else check SRRQ.

;Terminate loop (enddo) and finish

;Store 24-bit data in P mem.

;movem cannot be at LA.

;and go get another 24-bit word.

;finish bootstrap

A-10

DSP56301 User’s Manual

Page 305 Page 307
Page 306
Image 306
Motorola DSP56301 user manual Lble
Page 305 Page 307

DSP56301 specifications

The Motorola DSP56301 is a highly efficient digital signal processor, specifically engineered for real-time audio and speech processing applications. This DSP is part of Motorola's renowned DSP56300 family, which is recognized for its innovative features and outstanding performance in the realm of digital signal processing.

One of the main features of the DSP56301 is its ability to handle complex computations at high speeds. With a maximum clock frequency of 66 MHz, it delivers fast performance, enabling it to process audio signals in real time. The chip is built on a 24-bit architecture, which allows for high-resolution audio processing. This is particularly beneficial in applications such as telecommunications, consumer audio devices, and professional audio equipment, where precision is paramount.

The DSP56301 boasts a comprehensive instruction set that includes efficient mathematical operations, which are essential for digital filters and audio effects processing. One of the key innovations of this device is its dual data path architecture, which permits simultaneous processing of multiple data streams. This feature significantly enhances the device's throughput and responsiveness, making it suitable for demanding applications such as voice recognition and synthesis.

In terms of memory regions, the DSP56301 includes several on-chip memory categories, such as program memory, data memory, and a specialized memory for coefficients. The architecture's support for external memory expansion further increases its versatility, allowing designers to tailor systems to their specific requirements.

The DSP56301 implements advanced features such as a powerful on-chip hardware multiplier and accumulator, simplifying complex mathematical tasks and accelerating the execution of algorithms. Its flexible interrupt system enhances its capability to respond to time-sensitive operations, while the integrated serial ports facilitate efficient data communication with external devices.

Power consumption is also a vital characteristic of the DSP56301. It is designed with energy efficiency in mind, allowing for extended operation in battery-powered devices. The chip’s low power requirements are particularly advantageous in portable audio devices and other applications where energy conservation is crucial.

In conclusion, the Motorola DSP56301 is an exceptional digital signal processor that combines high processing power, flexibility, and efficiency. Its main features, advanced technologies, and robust architecture make it a top choice for developers seeking to create sophisticated audio and signal processing systems. With its enduring legacy in the industry, the DSP56301 continues to be relevant in a variety of modern applications, ensuring it remains a valuable tool for engineers and designers.