HI32 DSP-Side Programming Model

when the host-to-DSP data path FIFO is emptied by DSP56300 core reads. The DSP56300 core can set the SRIE bit to cause a host receive data interrupt when SRRQ is set.

In 32-bit mode (DCTR[HM] = $1 with DPMC[FC] = $0 or HCTR[HTF] = $0), only the two least significant bytes contain data. The most significant byte is read as zeroes. (See Table

6-3). Hardware, software, and personal software resets empty the host-to-DSP data path FIFO (SRRQ and MRRQ are cleared).

6.7.8DSP Master Transmit Data Register (DTXM)

The 24-bit wide DSP Master Transmit Data Register (DTXM) is the input stage of the master DSP-to-host data path FIFO for DSP-to-host master data transfers in PCI mode (DCTR[HM]

=$1). The DTXM can be written if the DPSR[MTRQ] bit is set. To prevent overwriting of

previous data, data should not be written to the DTXM until DPSR[MTRQ] is set. Filling the DTXM by DSP56300 core writes (MOVE(P) instructions or DMA transfers) clears DPSR[MTRQ]. The DSP56300 core can set the DPCR[MTIE] bit to cause a host receive data interrupt when DPSR[MTRQ] is set.

In PCI mode (DCTR[HM] = $1), the DSP56300 core can clear the HI32 master-to-host bus data path and empty DTXM by setting DPCR[CLRT]. In 32-bit mode (DCTR[HM] = $1 with DPMC[FC] = $0), only the two least significant bytes of the DTXM are transferred. (See Table 6-3). Hardware, software and personal software resets empty the DTXM.

6.7.9DSP Slave Transmit Data Register (DTXS)

The 24-bit wide DSP Slave Transmit Data Register (DTXS) is the input stage of the slave DSP-to-host data path FIFO for DSP-to-host slave data transfers in PCI mode (DCTR[HM] = $1).

The DTXS can be written if the DSR[STRQ] bit is set. To prevent overwriting of previous data, data should not be written to the DTXS until DSR[STRQ] is set. Filling the DTXS by DSP56300 core writes (MOVE(P) instructions or DMA transfers) clears DSR[STRQ]. The DSP56300 core can set the STIE bit to cause a host receive data interrupt when DSR[STRQ] is set. In 32-bit mode (DCTR[HM] = $1 with HCTR[HRF] = $0), only the two least significant bytes of the DTXS are transferred. (See Section 6.3.2, DSP-To-Host Data Path, on page 6-7, and Table 6-3,HI32 (PCI Master Data Transfer Formats, on page 6-8). Hardware, software and personal software resets empty the DTXS.

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DSP56301 specifications

The Motorola DSP56301 is a highly efficient digital signal processor, specifically engineered for real-time audio and speech processing applications. This DSP is part of Motorola's renowned DSP56300 family, which is recognized for its innovative features and outstanding performance in the realm of digital signal processing.

One of the main features of the DSP56301 is its ability to handle complex computations at high speeds. With a maximum clock frequency of 66 MHz, it delivers fast performance, enabling it to process audio signals in real time. The chip is built on a 24-bit architecture, which allows for high-resolution audio processing. This is particularly beneficial in applications such as telecommunications, consumer audio devices, and professional audio equipment, where precision is paramount.

The DSP56301 boasts a comprehensive instruction set that includes efficient mathematical operations, which are essential for digital filters and audio effects processing. One of the key innovations of this device is its dual data path architecture, which permits simultaneous processing of multiple data streams. This feature significantly enhances the device's throughput and responsiveness, making it suitable for demanding applications such as voice recognition and synthesis.

In terms of memory regions, the DSP56301 includes several on-chip memory categories, such as program memory, data memory, and a specialized memory for coefficients. The architecture's support for external memory expansion further increases its versatility, allowing designers to tailor systems to their specific requirements.

The DSP56301 implements advanced features such as a powerful on-chip hardware multiplier and accumulator, simplifying complex mathematical tasks and accelerating the execution of algorithms. Its flexible interrupt system enhances its capability to respond to time-sensitive operations, while the integrated serial ports facilitate efficient data communication with external devices.

Power consumption is also a vital characteristic of the DSP56301. It is designed with energy efficiency in mind, allowing for extended operation in battery-powered devices. The chip’s low power requirements are particularly advantageous in portable audio devices and other applications where energy conservation is crucial.

In conclusion, the Motorola DSP56301 is an exceptional digital signal processor that combines high processing power, flexibility, and efficiency. Its main features, advanced technologies, and robust architecture make it a top choice for developers seeking to create sophisticated audio and signal processing systems. With its enduring legacy in the industry, the DSP56301 continues to be relevant in a variety of modern applications, ensuring it remains a valuable tool for engineers and designers.
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