ESSI Data and Control Signals

Table 7-2.Mode and Signal Definitions

 

 

 

Control Bits

 

 

 

 

 

 

ESSI Signals

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SYN

 

TE0

 

TE1

 

TE2

RE

 

SC0

 

SC1

SC2

SCK

STD

SRD

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

 

0

 

X

 

X

0

 

U

 

U

U

U

U

U

0

 

0

 

X

 

X

1

 

RXC

 

FSR

U

U

U

RD

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

 

1

 

X

 

X

0

 

U

 

U

FST

TXC

TD0

U

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

 

1

 

X

 

X

1

 

RXC

 

FSR

FST

TXC

TD0

RD

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

 

0

 

0

 

0

0

 

U

 

U

U

U

U

U

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

 

0

 

0

 

0

1

 

F0/U

 

F1/T0D/U

FS

XC

U

RD

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

 

0

 

0

 

1

0

 

F0/U

 

TD2

FS

XC

U

U

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

 

0

 

0

 

1

1

 

F0/U

 

TD2

FS

XC

U

RD

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

 

0

 

1

 

0

0

 

TD1

 

F1/T0D/U

FS

XC

U

U

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

 

0

 

1

 

0

1

 

TD1

 

F1/T0D/U

FS

XC

U

RD

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

 

0

 

1

 

1

0

 

TD1

 

TD2

FS

XC

U

U

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

 

0

 

1

 

1

1

 

TD1

 

TD2

FS

XC

U

RD

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

 

1

 

0

 

0

0

 

F0/U

 

F1/T0D/U

FS

XC

TD0

U

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

 

1

 

0

 

0

1

 

F0/U

 

F1/T0D/U

FS

XC

TD0

RD

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

 

1

 

0

 

1

0

 

F0/U

 

TD2

FS

XC

TD0

U

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

 

1

 

0

 

1

1

 

F0/U

 

TD2

FS

XC

TD0

RD

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

 

1

 

1

 

0

0

 

TD1

 

F1/T0D/U

FS

XC

TD0

U

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

 

1

 

1

 

0

1

 

TD1

 

F1/T0D/U

FS

XC

TD0

RD

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

 

1

 

1

 

1

0

 

TD1

 

TD2

FS

XC

TD0

U

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

 

1

 

1

 

1

1

 

TD1

 

TD2

FS

XC

TD0

RD

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TXC

=

Transmitter clock

 

 

 

 

 

 

 

 

 

 

RXC

=

Receiver clock

 

 

 

 

 

 

 

 

 

 

XC

= Transmitter/receiver clock (synchronous operation)

 

 

 

 

 

FST

=

Transmitter frame sync

 

 

 

 

 

 

 

 

 

FSR

=

Receiver frame sync

 

 

 

 

 

 

 

 

 

FS

= Transmitter/receiver frame sync (synchronous operation)

 

 

 

 

TD0

= Transmit data signal 0

 

 

 

 

 

 

 

 

 

TD1

= Transmit data signal 1

 

 

 

 

 

 

 

 

 

TD2

= Transmit data signal 2

 

 

 

 

 

 

 

 

 

T0D

= Transmitter 0 drive enable if SSC1 = 1 & SCD1 = 1

 

 

 

 

 

RD

=

Receive data

 

 

 

 

 

 

 

 

 

 

F0

=

Flag 0

 

 

 

 

 

 

 

 

 

 

F1

= Flag 1 if SSC1 = 0

 

 

 

 

 

 

 

 

 

 

U

= Unused (can be used as GPIO signal)

 

 

 

 

 

 

 

X

=

Indeterminate

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

When configured as an output, SC1 functions as a serial Output Flag, as the transmitter 0 drive-enabled signal, or as the receive frame sync signal output. If SC1 is used as serial Output Flag 1, its value is determined by the value of the serial Output Flag 1 (OF1) bit in the CRB. When configured as an input, this signal can receive frame sync signals from an external source, or it acts as a serial input flag. As a serial input flag, SC1controls status bit IF1 in the SSISR.

When SC1 is configured as a transmit data signal, it is always an output signal, regardless of the SCD1 bit value. As an output, it is fully synchronized with the other ESSI transmit data signals (STD and SC0). SC1 can be programmed as a GPIO signal (P1) when the ESSI SC1 function is not in use.

Enhanced Synchronous Serial Interface (ESSI)

7-5

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Motorola DSP56301 Mode and Signal Definitions, Control Bits Essi Signals, SYN TE0 TE1 TE2 SC0 SC1 SC2 SCK STD SRD

DSP56301 specifications

The Motorola DSP56301 is a highly efficient digital signal processor, specifically engineered for real-time audio and speech processing applications. This DSP is part of Motorola's renowned DSP56300 family, which is recognized for its innovative features and outstanding performance in the realm of digital signal processing.

One of the main features of the DSP56301 is its ability to handle complex computations at high speeds. With a maximum clock frequency of 66 MHz, it delivers fast performance, enabling it to process audio signals in real time. The chip is built on a 24-bit architecture, which allows for high-resolution audio processing. This is particularly beneficial in applications such as telecommunications, consumer audio devices, and professional audio equipment, where precision is paramount.

The DSP56301 boasts a comprehensive instruction set that includes efficient mathematical operations, which are essential for digital filters and audio effects processing. One of the key innovations of this device is its dual data path architecture, which permits simultaneous processing of multiple data streams. This feature significantly enhances the device's throughput and responsiveness, making it suitable for demanding applications such as voice recognition and synthesis.

In terms of memory regions, the DSP56301 includes several on-chip memory categories, such as program memory, data memory, and a specialized memory for coefficients. The architecture's support for external memory expansion further increases its versatility, allowing designers to tailor systems to their specific requirements.

The DSP56301 implements advanced features such as a powerful on-chip hardware multiplier and accumulator, simplifying complex mathematical tasks and accelerating the execution of algorithms. Its flexible interrupt system enhances its capability to respond to time-sensitive operations, while the integrated serial ports facilitate efficient data communication with external devices.

Power consumption is also a vital characteristic of the DSP56301. It is designed with energy efficiency in mind, allowing for extended operation in battery-powered devices. The chip’s low power requirements are particularly advantageous in portable audio devices and other applications where energy conservation is crucial.

In conclusion, the Motorola DSP56301 is an exceptional digital signal processor that combines high processing power, flexibility, and efficiency. Its main features, advanced technologies, and robust architecture make it a top choice for developers seeking to create sophisticated audio and signal processing systems. With its enduring legacy in the industry, the DSP56301 continues to be relevant in a variety of modern applications, ensuring it remains a valuable tool for engineers and designers.