Motorola DSP56301 DSP Status Register DSR Bit Definitions, 2322212019181716, HI32 Active

HI32 DSP-Side Programming Model

6.7.5DSP Status Register (DSR)

.

2322212019181716

HACT

UBM

PCI

SC

15	14	13	12	11	10	9	8
7	6	5	4	3	2	1	0
		HF2	HF1	HF0	SRRQ	STRQ	HCP
		UBM	UBM	UBM	UBM	UBM	UBM
		PCI	PCI	PCI	PCI	PCI	PCI
	Reserved. Write to 0 for future compatibility
UBM = Universal Bus mode		PCI = PCI mode	SC = Self-Configuration mode

Figure 6-9.DSP Status Register (DSR)

A 24-bit read-only status register by which the DSP56300 core examines the HI32 status and flags. The host processor cannot access DSR.

Note: When data is written to the HI32, there is a two-cycle pipeline delay while any status bits affected by this operation are updated. If any of the status bits are read during the two-cycle delay, the status bit may not reflect the current status.

Table 6-14.DSP Status Register (DSR) Bit Definitions

Bit	Bit Name	Reset	Mode	Description
Number		Value
23	HACT	0	UBM	HI32 Active
			PCI	Indicates the activity of the HI32. HACT is set when DCTR[HM] = $1,
			SC	$2, $3, or $5. HACT is cleared in response to Terminate and Reset
				(DCTR[HM] = $0):
				ν While the HI32 is an active PCI bus master or selected target in a
				memory space transaction, a master-initiated termination or
				target disconnect, respectively, is generated. When the PCI idle
				state is detected, HACT is cleared.
				ν While the HI32 is in a Universal Bus or Self-Configuration mode
				(DCTR[HM] = $2, $3 or $5), the HACT status bit in the DSR is
				cleared immediately.
				When HACT is set, the HI32 is active, and the DCTR mode and polarity
				bits must not be changed.
22–6		0		Reserved. Write to 0 for future compatibility.

Host Interface (HI32) 6-35