Index-11

PCI-only registers

DSP PCI Address Register (DPAR) 6-33

DSP PCI Master Control Register (DPMC) 6-30DSP PCI Port Control Register (DPCR) 6-26DSP PCI Status Register (DPSR) 6-38

Peripheral Component Interconnect (PCI) 1-5configuration registers 6-44

illegal events 6-46

PCI Specification Revision 2.0 6-1Peripheral I/O Expansion Bus 1-10peripheral programming 5-1personal software reset state 6-12

HI32 6-12Phase-Lock Loop (PLL) 2-5

signals 2-1,2-5

Phase-Lock Loop (PLL) Initial (PINIT) state 2-5PINIT 4-21

PLL 1-9

PLL Capacitor (PCAP) 2-5

PLL Control (PCTL) register 4-21Clock Output Disable (COD) 4-21Crystal Range (XTLR) 4-21Division Factor (DF) 4-21

PLL Enable (PEN) 4-21

PLL Multiplication Factor (MF) 4-21PLL Stop State (PSTP) 4-21Predivider Factor (PD) 4-21programming sheet B-17

XTAL Disable (XTLD) 4-21PLL Enable (PEN) bit 4-21PLL Stop State (PSTP) bit 4-21polling 5-2

Port A 2-6,4-22Port B 5-5

GPIO 2-3,5-5programming sheet B-40

Port C 2-2,2-23,5-6control registers 7-36

Port C Control Register (PCRC) 7-36programming sheet B-41

Port C Data Register (PDRC) 7-38programming sheet B-41

Port C Direction Register (PRRC) 7-37programming sheet B-41

Port D 2-2,2-25,5-6control registers 7-36

Port D Control Register (PCRD) 7-36programming sheet B-42

Port D Data Register (PDRD) 7-38programming sheet B-42

Port D Direction Register (PRRD) 7-37programming sheet B-42

Port E 2-27,5-6

Port E Control Register (PCRE) 8-24

programming sheet B-43Port E Data Register (PDRE) 8-25

programming sheet B-43

Port E Direction Register (PRRE) 8-25programming sheet B-43

Position Independent Code (PIC) support 1-4power 2-1,2-4

Predivider Factor (PD) bits 4-21Pre-Fetch (PF) bit 6-71prescale divider for ESSI 7-16Prescale Modulus Select (PM) bits 7-16Prescaler Clock Enable (PCE) bit 9-29prescaler counter 9-25

Prescaler Counter Value (PC) bits 9-28Prescaler Preload Value (PL) bits 9-27Prescaler Range (PSR) bit 7-16Prescaler Source (PS) bits 9-27Program Address Bus (PAB) 1-10Program Address Generator (PAG) 1-8Program Control Unit (PCU) 1-4,1-8Program Counter (PC) register 1-8Program Data Bus (PDB) 1-10Program Decode Controller (PDC) 1-8Program Interrupt Controller (PIC) 1-8program memory 1-5,3-2

internal 3-1

program memory expansion 1-5Program ROM, bootstrap 3-1programming model

ESSI 7-14HI32

DSP side 6-22host side 6-44

SCI 8-9timer 9-25

programming peripherals 5-1

Read (RD) 2-7

Read Address Strobe 0–3 ( RAS[0–3]) 2-6Receive Buffer Lock Enable (RBLE) bit 6-27Receive Clock Mode Source (RCM) 8-19Receive Data (RXD) signal 8-4

Receive Data Register (RX) 7-30

Receive Data Register Full (RDF) bit 7-28Receive Data Register Full (RDRF) bit 8-18Receive Enable (RE) bit 7-20

Receive Exception Interrupt Enable (REIE) bit 7-19Receive Frame Sync Flag (RFS) 7-29

Receive Interrupt Enable (RIE) bit 7-19

Receive Last Slot Interrupt Enable (RLIE) bit 7-19Receive Request Enable (RREQ) bit 6-55Receive Shift Register 7-29

DSP56301 specifications

The Motorola DSP56301 is a highly efficient digital signal processor, specifically engineered for real-time audio and speech processing applications. This DSP is part of Motorola's renowned DSP56300 family, which is recognized for its innovative features and outstanding performance in the realm of digital signal processing.

One of the main features of the DSP56301 is its ability to handle complex computations at high speeds. With a maximum clock frequency of 66 MHz, it delivers fast performance, enabling it to process audio signals in real time. The chip is built on a 24-bit architecture, which allows for high-resolution audio processing. This is particularly beneficial in applications such as telecommunications, consumer audio devices, and professional audio equipment, where precision is paramount.

The DSP56301 boasts a comprehensive instruction set that includes efficient mathematical operations, which are essential for digital filters and audio effects processing. One of the key innovations of this device is its dual data path architecture, which permits simultaneous processing of multiple data streams. This feature significantly enhances the device's throughput and responsiveness, making it suitable for demanding applications such as voice recognition and synthesis.

In terms of memory regions, the DSP56301 includes several on-chip memory categories, such as program memory, data memory, and a specialized memory for coefficients. The architecture's support for external memory expansion further increases its versatility, allowing designers to tailor systems to their specific requirements.

The DSP56301 implements advanced features such as a powerful on-chip hardware multiplier and accumulator, simplifying complex mathematical tasks and accelerating the execution of algorithms. Its flexible interrupt system enhances its capability to respond to time-sensitive operations, while the integrated serial ports facilitate efficient data communication with external devices.

Power consumption is also a vital characteristic of the DSP56301. It is designed with energy efficiency in mind, allowing for extended operation in battery-powered devices. The chip’s low power requirements are particularly advantageous in portable audio devices and other applications where energy conservation is crucial.

In conclusion, the Motorola DSP56301 is an exceptional digital signal processor that combines high processing power, flexibility, and efficiency. Its main features, advanced technologies, and robust architecture make it a top choice for developers seeking to create sophisticated audio and signal processing systems. With its enduring legacy in the industry, the DSP56301 continues to be relevant in a variety of modern applications, ensuring it remains a valuable tool for engineers and designers.

Motorola DSP56301 user manual Index-11

Models: DSP56301

Index-11

DSP56301 specifications