Jtag Identification ID Register | Motorola DSP56301 guide

JTAG Identification (ID) Register

4.9JTAG Identification (ID) Register

The JTAG ID register is a 32-bit read-only factory-programmed register that distinguishes the component on a board according to the IEEE 1149.1 standard. Figure 4-11shows the JTAG ID register configuration. Version information corresponds to the revision number ($0 for revision 0, $1 for revision A, and so forth).

I)
31	28	27	22	21	12	11	1	0

Version Information		Design Center			Sequence		Manufacturer	1
Version Information			Number		Number		Identity	1
			Number		Number		Identity

	See Note		000110	0000000011			00000001110	1

Note:	No specific revision number is shown because this manual is current for several versions of the DSP56301.

Figure 4-11.JTAG Identification (ID) Register Configuration

4.10JTAG Boundary Scan Register (BSR)

The BSR in the DSP56301 JTAG implementation contains bits for all device signals, clock pins, and their associated control signals. All DSP56301 bidirectional pins have a corresponding register bit in the BSR for pin data and are controlled by an associated control bit in the BSR. For details on the BSR, consult the DSP56300 Family Manual. For the latest description of the BSR contents by available package type in boundary scan description language (BSDL), call your local Motorola Semiconductor Sales Office or authorized distributor, or refer to the following Motorola website:

http://www.mot.com/SPS/DSP/tools/other.html#56303

Core Configuration

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Motorola DSP56301 Jtag Identification ID Register, Jtag Boundary Scan Register BSR, Version Information Design Center

DSP56301 specifications

The Motorola DSP56301 is a highly efficient digital signal processor, specifically engineered for real-time audio and speech processing applications. This DSP is part of Motorola's renowned DSP56300 family, which is recognized for its innovative features and outstanding performance in the realm of digital signal processing.

One of the main features of the DSP56301 is its ability to handle complex computations at high speeds. With a maximum clock frequency of 66 MHz, it delivers fast performance, enabling it to process audio signals in real time. The chip is built on a 24-bit architecture, which allows for high-resolution audio processing. This is particularly beneficial in applications such as telecommunications, consumer audio devices, and professional audio equipment, where precision is paramount.

The DSP56301 boasts a comprehensive instruction set that includes efficient mathematical operations, which are essential for digital filters and audio effects processing. One of the key innovations of this device is its dual data path architecture, which permits simultaneous processing of multiple data streams. This feature significantly enhances the device's throughput and responsiveness, making it suitable for demanding applications such as voice recognition and synthesis.

In terms of memory regions, the DSP56301 includes several on-chip memory categories, such as program memory, data memory, and a specialized memory for coefficients. The architecture's support for external memory expansion further increases its versatility, allowing designers to tailor systems to their specific requirements.

The DSP56301 implements advanced features such as a powerful on-chip hardware multiplier and accumulator, simplifying complex mathematical tasks and accelerating the execution of algorithms. Its flexible interrupt system enhances its capability to respond to time-sensitive operations, while the integrated serial ports facilitate efficient data communication with external devices.

Power consumption is also a vital characteristic of the DSP56301. It is designed with energy efficiency in mind, allowing for extended operation in battery-powered devices. The chip’s low power requirements are particularly advantageous in portable audio devices and other applications where energy conservation is crucial.

In conclusion, the Motorola DSP56301 is an exceptional digital signal processor that combines high processing power, flexibility, and efficiency. Its main features, advanced technologies, and robust architecture make it a top choice for developers seeking to create sophisticated audio and signal processing systems. With its enduring legacy in the industry, the DSP56301 continues to be relevant in a variety of modern applications, ensuring it remains a valuable tool for engineers and designers.

Contents

Revision 3, March DSP56301 User’s Manual USA/EUROPE How to reach usJapan ASIA/PACIFICPage Page Contents Chapter Core Configuration Chapter Memory Configuration Chapter Host Interface HI32 Chapter Programming the Peripherals Chapter Enhanced Synchronous Serial Interface Essi Chapter Serial Communication Interface SCI Chapter a Bootstrap Program Chapter B Programming Reference Chapter Triple Timer ModuleIndex DSP56301 User’s Manual Figures Xii Pulse Width Modulation Toggle Mode, TRM = DSP Control Register Dctr DSP PCI Control Register Dpcr Tables Tables Essi Clock Sources Overview Manual Organization Signal/Symbol Logic State Signal State Voltage High True/Low True Signal ConventionsManual Conventions Ground2 PIN is a generic term for any pin on the chip Ground DSP56300 Core Features CE = MS = Program RAM Instruction Data RAM Switch Size Cache SizeSize Cache Data ALU DSP56300 Core Functional Blocks Data ALU Registers Address Generation Unit AGUMultiplier-Accumulator MAC Program Control Unit PCU Jtag TAP and OnCE Module PLL and Clock Oscillator Internal Buses DSP56301 Switch Memory ConfigurationOn-Chip Memory Memory Expansion Area DMAExpansion Area Peripherals General-Purpose Input/Output Gpio signalsHost Interface HI32 Enhance Synchronous Serial Interface Essi Serial Communications Interface SCI Triple Timer Module DSP56301 Documentation Related Documents and Web SitesName Description Order Number DSP56300FM/AD Timers JTAG/OnCE Port DSP56301 Functional Signal GroupingsEnhanced Synchronous Serial Interfaces ESSI0 ESSI1 DSP56301 See -2for a listing of the Host Interface/Port B SignalsPort a Host Interface/Port B Detail Signal Diagram Power Inputs PowerGround Signals Ground Phase-Lock Loop Signals Clock SignalsClock PLL External Address Bus External Memory Expansion Port Port aExternal Data Bus External Bus Control Arbitration is reset to the bus slave state Signals are tri-statedOutput Tri-stated Is an active-low output that is Output Tri-stated Is asserted for half a clock Bclk CAS Interrupt and Mode Control Interrupt and Mode ControlSignal State Type During Signal Description Name Nonmaskable Interrupt-After 10.Host Interface Host Interface HI32 Command 0-3/Byte Enable 0-3 -When the HI32 is programmed Hpar HBSHdak Hperr Hirq HserrHstop HWR Signal PCI Mode Enhanced Universal Bus Mode Gpio Mode Name 11.Summary of HI32 Signals and Modes HAD10 HD2 HIO10 HP8 HAD8 HD0 HIO8 HP9 HAD9 HD1 HIO9HAD11 HD3 HIO11 HAD12 HD4 HIO12 PCI 12.Host Port Pins HI32Gpio Host Target Ready Host Data Bus Enable Bus Command/Byte Enable Host Address BusReserved Host Initiator Ready Host Data Bus Direction Bus Grant Host Address Enable Parity Error DMA RequestHost Device Select Host Select Acknowledge Host Lock Bus Strobe Bus Request Host Transfer Acknowledge Host System Error Host Interrupt RequestHreq is deasserted in the same PCI Hstr Host Stop Host Write/Read-Write Hstop HWR/HRWHRD/HDS Initialization Device Select Host Read/Data Strobe Address/Data Multiplexed Bus Data Bus Host Bus Clock Enhanced Synchronous Serial Interface Hardware ResetHost Interrupt a Active low, open drain output pin PC0 13.Enhanced Synchronous Serial InterfacePC1 PC2 PC3 SCK0SRD0 PC4 PD0 14.Enhanced Serial Synchronous InterfacePD1 PD2 PD3 SCK1SRD1 PD4 Serial Communications Interface SCI Timers15.Serial Communication Interface Timer 0 Schmitt-Trigger Input/Output- When Timer 16.Triple Timer SignalsTimer 1 Schmitt-Trigger Input/Output- When Timer Timer 2 Schmitt-Trigger Input/Output- When timer Jtag and OnCE Interface Signal Name Type State During Signal Description Reset17.JTAG/OnCE Interface Jtag and OnCE Interface DSP56301 User’s Manual Program Memory Space Memory Configuration Internal Program Memory Memory Switch Modes-Program MemoryInstruction Cache Memory Switch Modes-X Data Memory Program Bootstrap ROMMemory Configuration Data Memory Space Internal I/O Space-X Data Memory Memory Switch Modes-Y Data MemoryInternal Y Data Memory External I/O Space-Y Data Memory Dynamic Memory Configuration Switching Internal Memory Configuration Summary Sixteen-Bit Compatibility Mode ConfigurationDSP56301 RAM Configurations DSP56301 RAM Address Ranges by Configuration Memory Maps DefaultRAM None 64K $000-$FFF $000-$7FF 16-Bit Space With Default RAM 0, 0 $000-$800 $000-$BFF 16M None 64K $000-$7FF $000-$BFF 16-Bit Space With Switched Program RAM 0, 1 $000-$BFF $000-$7FF Not addressable Instruction Cache Enabled 1, 0 16-Bit Space With Instruction Cache Enabled 1, 0 $000-$3FF $000-$BFF Not addressable Addressable $0400 $0000 Core Configuration Core Configuration Operating Modes Reset Description VectorDSP56301 Operating Modes Mode Mode Description Operating Mode Definitions Low. The DSP56301 is written with 24-bit-wide words Address attributes selected defaultDSP Clkout rate must be 5/3 of the PCI clock Bootstrap Program Status Register SR Central Processor Unit CPU Registers DMA OMR Sixteen-Bit Arithmetic Mode Cache EnableDo Forever Flag Do Loop Flag Sixteen-Bit Compatibility Mode Scaling Rounding Bit SEquation Mode Scaling ModeInterrupt Mask Priority Exceptions Exceptions Masked Permitted Scaling Mode Integer Portion Bit Number Bit Name Reset Value Description LimitExtension Unnormalized Operating Mode Register OMR Bit Definitions Operating Mode Register OMRStack Extension Enable Stack Extension Wrap Flag Address Attribute Priority Disable Address Trace EnableAsynchronous Bus Arbitration Enable Stack Extension Overflow Flag Memory Switch Mode Cache Burst Mode EnableBus Release Timing Synchronize Select Bit Number Bit Name Reset Value Description Stop Delay Mode Configuring InterruptsExternal Bus Disable Chip Operating Mode Interrupt Priority Registers Iprc and Iprp Interrupt Priority Level Bits Interrupt Table Memory MapInterrupt Sources VBA$1C VBA$1AVBA$1E VBA$2A Interrupt Source Priorities Within an IPL Processing Interrupt Source Priorities Within an IPLPriority Interrupt Source TIMER0 overflow interrupt Host command interruptTIMER0 compare interrupt TIMER1 overflow interrupt PLL Control Register Pctl Bit Definitions PLL Control Register Pctl Bus Control Register Bus Interface Unit BIU Registers Bus Area 3 Wait State Control Bus Default Area Wait State ControlBus Area 2 Wait State Control Bus Area 1 Wait State Control BRP BRF7 BRF6 Dram Control Register DCRBRF3 BRF2 BRF1 Bstr Bren BME Bple BPS1 10.DRAM Control Register DCR Bit Definitions Bus Dram Page Size Bus Page Logic EnableBus Row Out-of-page Wait States Bus Column In-Page Wait State Bus Address to Compare Address Attribute Registers AAR0-3Bus Number of Address Bits to Compare Bus Y Data Memory Enable Bus Packing EnableBus X Data Memory Enable Bus Program Memory Enable DIE DTM2 DTM1 DTM0 DMA Control Registers 5-0 DCR5-0Dcon DAM5 DAM4 DAM3 DAM2 DAM1 DAM0 DMA Transfer Mode DMA Interrupt EnableDTM2-0 Trigger Cleared Transfer Mode After 12.DMA Control Register DCR Bit Definitions DMA Channel Priority Number ValueDMA address generation logic, buses, and so forth DPR1-0 Channel Priority OMR CDP1-0 CP1-0 Core Priority DMA Continuous Mode EnableDcon DMA Request Source Three-Dimensional ModeDRS4-0 Requesting Device DDS1 DDS0 Device Identification Register IDRDSS1 DSS0 Jtag Boundary Scan Register BSR Jtag Identification ID RegisterVersion Information Design Center Number Identity See Note Jtag Boundary Scan Register BSR DSP56301 User’s Manual Programming the Peripherals Peripheral Initialization Steps Data Transfer Methods Mapping the Control RegistersPolling Data Memory Interrupts 3 DMA General-Purpose Input/Output GpioAdvantages and Disadvantages Port B Signals and Registers Port D Signals and Registers Port C Signals and RegistersPort E Signals and Registers Timer Gpio Triple Timer Signals and Registers General-Purpose Input/Output Gpio DSP56301 User’s Manual Host Interface HI32 Features HI32 Features, Core-Side and Host-Side HI32 Features in PCI Mode and Universal Bus Mode Overview DSP-Side Registers PCI Configuration SpaceDSP DMA Data Bus DSP Global Data Bus Data transfer format converter Host-to-DSP Data Path Data Transfer Paths DSP-To-Host Data Path Dpmc HI32 PCI Master Data Transfer FormatsFC1 FC0 Two least significant bytes of two Hrxm Hctr Transmit Data Transfer FormatHTF1 HTF0 DSP to Host Data Transfer Format Receive Transfer Data FormatsHRF Three least significant Hrxs bytes Receive Transfer Data Formats Type Entered when Description Reset StatesDSP-Side Operating Modes HRST/HRST PCI Mode Dctrhm = $1 Terminate and Reset Dctrhm = $0HI32 Mode PCI Example 6-1. PCI /DMA Throughput 32-Bit Multfactor Self-Configuration Mode Dctrhm = $5 Gpio Mode Dctrhm = $4 Example 6-3. Self-Configuration Procedure for PCI Mode PCI Bus Universal Bus Mode Host Port PinsHost Port Pin Functionality DSP56301 ISA Slave Master HI32 DSP-Side Programming Model Memory Register Address ModeHI32 Programming Model, DSP Side DSP Control Register Dctr Mode Description ValueBit Number Bit Name 10.DSP Control Register Dctr Bit Definitions Htap Host Data Strobe ModeHost Transfer Acknowledge Polarity Host Read/Write Polarity Slave Transmit Interrupt Enable Slave Receive Interrupt EnableHost Command Interrupt Enable DSP PCI Control Register Dpcr Receive Buffer Lock Enable Insert Address Enable11.DSP PCI Control Register Dpcr Bit Definitions IAE Master Access Counter Enable Master Wait State DisableForce Hserr Transaction Termination Interrupt Enable Transfer Complete Interrupt EnableTransaction Abort Interrupt Enable Parity Error Interrupt Enable BL4 DSP PCI Master Control Register DpmcBL1 BL0 Data Transfer Format Control 12.DSP PCI Master Control Register Dmpc Bit DefinitionsA PCI DSP-to-Host transaction A PCI Host-to-DSP transaction DSP PCI Transaction Address High PCI Data Burst Length 13.DSP PCI Address Register Dpar Bit Definitions DSP PCI Address Register DparBE2 BE1 AR9 AR8 AR7 AR6 AR5 AR4 AR3 AR2 AR1 AR0 C3-0 Command Type PCI Bus CommandDSP PCI Transaction Address Low AR1 AR0 DSP Status Register DSR Bit Bit Name Reset Mode Description Number Value14.DSP Status Register DSR Bit Definitions 2322212019181716 Slave Receive Data Request Srrq UBM Host Command Pending Mode Description Number Value14. DSP Status Register DSR Bit Definitions Slave Transmit Data Request 15.DSP PCI Status Register Dpsr Bit Definitions DSP PCI Status Register DpsrRdcq MDT Hdtc Trty Tdis TAB MAB Aper Marq Mrrq Mtrq MWS PCI Host Data Transfer Complete Master Data TransferredPCI Time Out Termination PCI Target Retry PCI Address Parity Error PCI Data Parity ErrorPCI Target Disconnect PCI Target Abort 15. DSP PCI Status Register Dpsr Bit Definitions DSP Receive Data Fifo DrxrPCI Master Wait States PCI Master Receive Data Request DSP Slave Transmit Data Register Dtxs DSP Master Transmit Data Register Dtxm DSP Host Port Gpio Data Register Dath DSP Host Port Gpio Direction Register Dirh16.DATH and Dirh Functionality 17.HI32 Programming Model, Host-Side Registers Host-Side Programming ModelMemory Register Host-Side Programming Model Executed as Command Type 18.PCI Bus CommandsHC3/HBE3-HC0/HBE0 Ignored 21. Host-Side Registers Universal Bus Mode Address Space 20. Host-Side Registers PCI Configuration Address Space19. Host-Side Registers PCI Memory Address Space 13.Host Interface Control Register Hctr 1 HI32 Control Register Hctr Target Wait State Disable Bit Bit Name Reset Mode Description Number22.Host Interface Control Register Hctr Bit Definitions Twsd PCI Host Receive Data Transfer Format Host Transmit Data Transfer Format SFT UBM Inserted AddressSlave Fetch Type Cleared when the DSP56300 core writes to Universal Bus mode Fetch SFT =Reset, and Strq and Hstrhrrq are cleared Data path is lost when the reset state is Dmae Haen Dmae UBMHirq Rreq UBM Receive Req uest EnableDmae Treq Rreq Hirq Pin Hdrq pin Hreq Hint HF5 HF4 HF3 Host Interface Status Register HstrTrdy UBM UBM UBM UBM UBM UBM PCI PCI PCI PCI PCI PCI Host Request 23.Host Interface Status Register Hstr Bit DefinitionsHost interrupt a Treq Rreq Hreq Host Transmit Data Request Host Receive Data RequestTransmitter Ready 15.Host Command Vector Register Hcvr Host Command Vector Register Hcvr Host Command Vector 24.Host Command Vector Register Hcvr Bit DefinitionsBit Bit Name Reset Value Mode Description Number Hnmi UBM When the DSP56300 core acknowledges the host command Host CommandHost Master Receive Data Register Hrxm Host Slave Receive Data Register Hrxs Host Transmit Data Register Htxr Universal Bus mode Dctrhm = $2 or $3 PCI Mode Dctrhm = $1 Status/Command Configuration Register CSTR/CCMR Device ID/Vendor ID Configuration Register CDID/CVIDDPE SSE RMA RTA STA DPR Fbbc Signaled System Error Detected Parity ErrorSignalled Target Abort Received Master Abort Wait Cycle Control hardwired to zero System Error EnableParity Error Response Bus Master Enable Class Code/Revision ID Configuration Register CCCR/CRID HT7 HT6 HT5 HT4 HT3 HT2 HT1 HT0 Header Type hardwired to $00HT7-0 Read-only bits that identify the layout of bytes $10-$3F Cache Line Size Latency Timer HighCcls Universal Bus Mode Base Address Memory Space Base Address Configuration Register CbmaPM8 PM7 PM6 PM5 PM4 MS1 MS0 MSI Memory Base Address High/Low Memory Base Address Low Hardwired to zeros 29. Memory Space Base Address Configuration Register CbmaPre-Fetch Hardwired to zero Memory Space Hardwired to zeros Example 6-5. Code for Setting the Csid IL5 IL4 Interrupt Line-Interrupt Pin Configuration RegisterCILPIL1 IL0 Maxlat HS PH PS HI32 Programming Model/Quick ReferenceDctr Hcie UBM Hrsp Clrt Dpcr MtieRble Dpar DpmcDSR HCP Hact Dper Dpsr AperHdtc Rdcq Dmae TreqISA/EISA SFT Hnmi HcvrHrxm Hrxs Cccr Ccmr RMAChty Cbma MSI Rsma Rsmb Tsma Tclk STD GDB DDB RclkTsmb TX0 CRA SC0 Essi Enhancements Serial Transmit Data Signal STD Essi Data and Control SignalsSerial Receive Data Signal SRD Serial Clock SCK Serial Control Signal SC1 Serial Control Signal SC0 Control Bits Essi Signals Mode and Signal DefinitionsSYN TE0 TE1 TE2 SC0 SC1 SC2 SCK STD SRD Essi After Reset Serial Control Signal SC2Operation Initialization Exceptions Operation Write data to all enabled transmit registers Operating Modes Normal, Network, and On-Demand Normal/Network/On-Demand Mode Selection Synchronous/Asynchronous Operating Modes Frame Sync Signal FormatFrame Sync Selection Word Length Frame Sync and Data Word Timing Frame Sync Length for Multiple DevicesFrame Sync Polarity Flags Byte Format LSB/MSB for the Transmitter Essi Control Register a CRA Essi Programming ModelWL2 WL1 WL0 ALC PM7 PM6 PM5 PM4 PM3 PM2 PM1 PM0 Select SC1 Essi Control Register a CRA Bit DefinitionsWord Length Control Essi Word Length Selection Frame Rate Divider Control Alignment ControlPrescaler Range Prescale Modulus Select Crbsyn = CRBTE1 CRBOF0 SSISRIF0Rclock Tclock Shfd Essi Control Register B CRBOF1 OF0 ESSI0 X$FFFFB6, ESSI1 X$FFFFA6 Essi Control Register B CRB Bit Definitions Receive Enable Transmit Interrupt EnableTransmit 0 Enable TIE Transmit 2 Enable Transmit 1 EnableMode Select Synchronous/Asynchronous FSL1 FSL0 OF1 Serial Control DirectionSerial Output Flag OF0 Serial Clock RX Frame Sync RX Serial Data Serial Clock RX, TX Frame Sync RX, TX Serial DataTX Frame Sync TX Serial Data Essi Bit CRB SYN Bit Operation SSI Control Register B CRB READ/WRITE Bit OperationReceiver Interrupt or DMA Request and Flags Set Frame Sync FSL0 = 0, FSL1 = Data Flags Frame Sync FSL0 = 0, FSL1 = Data Out Flags Transmitter Underrun Error Flag Receiver Overrun Error FlagEssi Status Register Ssisr Receive Data Register Full Receive Frame Sync Flag Essi Receive Shift RegisterTransmit Frame Sync Flag Serial Input Flag Essi Transmit Shift Registers Essi Receive Data Register RX Transmit Registers Receive Registers WL0 Transmit Middle Byte Transmit Low Byte Register 24 BitLeast Significant MSB Essi Time Slot Register TSR Essi Transmit Data Registers TX2-0Transmit Slot Mask Registers TSMA, Tsmb TS9 TS8 TS7 TS6 TS5 TS4 TS3 TS2 TS1 TS0 15.ESSI Transmit Slot Mask Register B Tsmb RS7 RS6 Receive Slot Mask Registers RSMA, RsmbRS1 RS0 RS15 RS14 RS13 RS12 RS11 RS10 Port Control Registers Pcrc and Pcrd Gpio Signals and Registers Port Direction Registers Prrc and Prrd Essi Port Signal ConfigurationsESSI0/ESSI1 20.Port Data Registers Pdrc X$FFFFBD Pdrd X $FFFFAD Port Data Registers Pdrc and Pdrd Serial Communication Interface SCI Serial Communication Interface SCI Asynchronous Mode Synchronous ModeMultidrop Mode Wired-OR Mode I/O SignalsAddress Mode Wakeup Transmitting Data and Address Characters Transmit Data TXD Receive Data RXDSCI Serial Clock Sclk SCI Registers After Reset SCI After ResetReie Sckp Stir Tmie TIE RIE Ilie Woms RWU Wake SBK Ssftd SCI Initialization Preamble, Break, and Data Transmission Priority Exceptions Bootstrap Loading Through the SCI Boot Mode 2 or a SCI Programming Model WDS2 WDS1 WDS0 Bit Synchronous Data Shift Register ModeBit Asynchronous 1 Start, 8 Data, 1 Stop Bit Asynchronous 1 Start, 8 Data, 1 Even Parity, 1 Stop SCI Data Word Formats Ssftd = 0 Reie SCI Control Register SCRStir Tmie TIE RIE Ilie Woms RWU Wake SBK Ssftd WDS2 SCI Transmit Interrupt Enable Timer Interrupt EnableSCI Receive Interrupt Enable Idle Line Interrupt Enable Wired-OR Mode Select Receiver EnableWoms Wakeup Mode Select Receiver Wakeup EnableSend Break SCI Shift Direction Word Select Mode Word FormatsWDS1 WDS0 SCI Status Register SCI Status Register SSR Bit Definitions SCI Status Register SSRIdle Rdrf Tdre Trne Tdre Idle Line FlagTransmitter Empty TCM RCM SCP COD SCI Clock Control Register SccrTCM RCM Sclk Divide by Bit CounterCD11-0 Sckp = 0 + Sckp = X1 Clock X16 Clock Sckp = RX, TX Data Ssftd = SCI Receive Register SRX SCI Data RegistersSCI Receive Data Shift Register SCI Transmit Register STX PE2 PE1 PE0 Port E Control Register PcreSclk TXD RXD Port E Data Register Pdre Port E Direction Register PrrePRRE1 PRRE0 PDRE1 PDRE0 Gpio Signals and Registers DSP56301 User’s Manual Triple Timer Module Triple Timer Module Individual Timer Block Diagram Triple Timer Module Block DiagramGDB Tpcr Timer Module Block Diagram Timer After Reset Timer Exceptions Timer Initialization TCSR0 Tcie Timer Gpio Mode Triple Timer ModesTC3 TC2 TC1 TC0 TIO TLR Mode 0 internal clock, no timer output TRM =TCR Tcpr Mode 1 internal clock TRM = Timer Pulse ModeOutput Pulse width = timer clock Period Mode 2 internal clock TRM = 1 first event Timer Toggle ModeToggle Timer = write preload = write compare Clock CLK/2 or prescale CLK = write preload Mode 2 internal clock TRM == write compare Clock CLK/2 or prescale CLK Mode 3 internal clock TRM = Timer Event Counter ModeInput External TIO Cpuclk + = write compare Clock 10.Event Counter Mode, TRM = Measurement Input Width Mode Signal Measurement ModesInput Input width Measurement Mode 4 internal clock TRM = 1 first event Mode 4 internal clock TRM = Mode 5 internal clock TRM = Measurement Input Period ModeFirst event = write preload = write compare Input period Measurement Internal May occur TOF=1 Counting, doesReads TCR period Mode 6 internal clock TRM = Measurement Capture ModeInterrupt Service reads TCR delay = M N clock periods Internal PWM Pulse Width Modulation PWM, ModePulse width modulation 16.Pulse Width Modulation Toggle Mode, TRM = Mode 7 internal clock TRM = 17.Pulse Width Modulation Toggle Mode, TRM = Watchdog Modes Watchdog Pulse ModePulse Watchdog Output Internal Software does not reset watchdog timer watchdog times out Mode 9 internal clock TRM == write preload First event Mode 10 internal clock TRM = Watchdog Toggle ModeWatchdog Output Toggle Special Cases Triple Timer Module Programming ModelDMA Trigger Prescaler Counter Register Tplr Timer Prescaler Load23 22 21 20 19 18 17 Tplr = $FFFF83 Prescaler Source Timer Prescaler Load Register TplrPS1 PS0 Prescaler Preload Value Timer Control/Status Register Tcsr Timer Prescaler Count Register TpcrTCF TOF PCE TRM INV Timer Overflow Flag Timer Compare FlagPrescaler Clock Enable Data Output Direction Timer Reload ModeInverter Number Function Timer Control Timer Overflow Interrupt Enable Timer Compare Interrupt EnableTimer Enable TIO Programmed as Input TIO Programmed as Output Mode INV = Pulse generated by Timer has Timer has negative Timer Load Register TLRPositive polarity Timer Count Register TCR Timer Compare Register Tcpr Appendix a DSP56301 User’s Manual HBS Can be stopped Hdben Aarv Mscte EQU LOOP0 Lbld Lble LOOP8 LOOP11 Rep Mac x0,x1,a x,lr0+ ORG PL,PL Patterns Write to Destination DSP56301 User’s Manual Programming Reference Chapter B Table B-1.Guide to Programming Sheets Table B-2. Internal I/O Memory Map X Data Memory Internal I/O Memory MapBit Address Register Name Peripheral Bit Address Register Name Table B-2.Internal I/O Memory Map X Data Memory $FFCC $FFFFCC $FFCD $FFFFCD$FFCB $FFFFCB $FFCA $FFFFCA $FFBB $FFFFBB Essi $FFBC $FFFFBC$FFBA $FFFFBA $FFB9 $FFFFB9 $FFAB $FFFFAB Essi $FFAC $FFFFAC$FFAA $FFFFAA $FFA9 $FFFFA9 $FFFF91 $FFFF92$FFFF90 $FF8F $FFFF8F Table B-3. Interrupt Sources Interrupt Sources and Priorities VBA$6A Table B-3.Interrupt SourcesVBA$6C VBA$6E Table B-4.Interrupt Source Priorities Within an IPL Nonmaskable Host Command Interrupt ESSI0 receive last slot interrupt Figure B-1.Status Register SR Programming Sheets Stop Delay External Bus DisableMemory Switch Mode Burst Mode Enable Irqc Mode Irqd ModeIrqb Mode Irqa Mode Host IPL Triple Timer IPLInterrupt Priority Register Iprp $FFFFFE Read/Write Crystal Range Bit Xtlr PLL Control Register Pctl $FFFFFD Read/Write Bus Control Register BCR $FFFFFB Read/Write Default Area Wait Control, BitsBus Request Hold, Bit Bus Lock Hold, Bit Dram Control Register DCR $FFFFFA Read/Write Bus Y Data Memory Enable, Bit Bus Packing Enable, BitBus X Data Memory Enable, Bit Bus Program Memory Enable, Bit DMA Control Registers DCR5-DCR0 Reset = $000000 $FFFFE4, X$FFFFE8, X$FFFFEC Read/Write Application DSP Control Register Dctr Read/Write Address X FFFFC5 DSP PCI Control Register Dpcr Address XFFFFC6 Read/Write = Enables master receive interrupts Figure B-12.DSP PCI Master Control Register Dpmc Figure B-13.DSP PCI Address Register Dpar PCI Bus Command, Bits HI32 Control Register Hctr Read/Write Host Non-Maskable Interrupt, Bit HI32 Command Vector Register Hcvr Read/Write Signaled System Error, Bit Detected Parity Error, BitSignalled Target Abort, Bit System Error Enable, Bit Read/Write Latency Timer High, BitsHeader Type, Bits Cache Line Size, Bits Reset = $00000000 HI32 Memory Space Base Address Configuration Register CbmaPCI Mode Base Address High, Bits Pre-fetch, Bit Memory Space Indicator, Bit Subsystem ID Register, Bits 31-16 Specifies the subsystem ID ESSI1-X$FFFFA5 Read/Write Essi Control Register a CRAx ESSI0-X$FFFFB5 Read/Write ESSI0-X$FFFFB6 Read/Write Essi Control Register B CRBxESSI1-X$FFFFA6 Read/Write ESSI1-X$FFFFA4 Read/Write Essi Transmit Slot Mask a TSMA0-1 ESSI0-X$FFFFB4 Read/WriteEssi Transmit Slot Mask B TSMB0-1 ESSI0-X$FFFFB3 Read/Write ESSI1-X$FFFFA3 Read/Write SCI Control Register SCR $FFFF9C Read/Write Receiver Clock Mode/Source SCI Clock Control Register Sccr Address X$FFFF9B Read/WriteClock Out Divider Timer Prescaler Load Register Tplr $FFFF83 Read/Write Figure B-25.Timer Prescaler Load Register Tplr TCSR1$FFFF8B Read/Write TCSR2$FFFF87 Read/Write Timer Control/Status Register TCSR0$FFFF8F Read/Write TLR1-X$FFFF8A Write Only TLR2-X$FFFF86 Write Only Timer Load Register TLR0-2 TLR0-X$FFFF8E Write Only Host Data Direction Register Hddr X$FFFFC8 Write Port B HI08Host Data Register HDR $FFFFC9 Write Port C Control Register Pcrc $FFFFBF Read/Write Port C ESSI0Port C Direction Register Prrc $FFFFBE Read/Write Port C Gpio Data Register Pdrc $FFFFBD Read/Write Port D Control Register Pcrd $FFFFAF Read/Write Port D ESSI1Port D Direction Register Prrd $FFFFAE Read/Write Port D Gpio Data Register Pdrd $FFFFAD Read/Write Port E Control Register Pcre $FFFF9F Read/Write Port E SCIPort E Direction Register Prre $FFFF9E Read/Write Port E Gpio Data Register Pdre $FFFF9D Read/Write Programming Sheets DSP56301 User’s Manual Index Index-2 DSP56301 User’s Manual Index-3 Index-4 DSP56301 User’s Manual Index-5 Index-6 DSP56301 User’s Manual Index-7 Index-8 DSP56301 User’s Manual Index-9 Index-10 DSP56301 User’s Manual Index-11 Index-12 DSP56301 User’s Manual Index-13 Index-14 DSP56301 User’s Manual Index-15 Index-16 DSP56301 User’s Manual

Motorola DSP56301 user manual Jtag Identification ID Register, Jtag Boundary Scan Register BSR

Models: DSP56301

4.9JTAG Identification (ID) Register

Version Information

Design Center

Sequence

Manufacturer

Number

Identity

See Note

Figure 4-11.JTAG Identification (ID) Register Configuration

4.10JTAG Boundary Scan Register (BSR)

Core Configuration

DSP56301 specifications