Htap, Host Transfer Acknowledge Polarity

HI32 DSP-Side Programming Model

Table 6-10.DSP Control Register (DCTR) Bit Definitions (Continued)

Bit Number

Bit Name

Reset

Mode

Description

Value

HTAP

Host Transfer Acknowledge Polarity

Controls the polarity of the HTA pin when the HI32 is in a Universal Bus

mode (DCTR[HM] = $2 or $3). If HTAP is cleared, the HTA pin is active

high and the HI32 requests to extend the access by driving the HTA pin

low (that is, deasserted). If HTAP is set, the HTA pin is active low and

the HI32 requests to extend the access by driving the HTA pin high (that

is, deasserted).

Note: HTA is driven in the Universal Bus modes (DCTR[HM] = $2 or

$3) while an external host is accessing the HI32. If the HI32 is

not accessed, the HTA pin is high impedance. The value of

HTAP can change only when DSR[HACT] = 0. HTAP is

ignored when the HI32 is not in a Universal Bus mode

(DCTR[HM] ≠ $2 or $3).

HRWP

Host Read/Write Polarity

Controls the polarity of

HWR/HRW signal in single-strobe Universal Bus

modes (DCTR[HM] = $2 or $3 and HDSM = 1); that is, when the

HWR/HRW signal (HP29) functions as the host read/write (HRW)

signal. When HRWP is cleared, the host-to-DSP data transfer direction

corresponds to the low level of the HRW signal, and DSP-to-host data

transfer direction corresponds to high level of the HRW signal. When

HRWP is set, the host-to-DSP data transfer direction corresponds to

the high level of the HRW signal, and DSP-to-host data transfer

direction corresponds to the low level of the HRW signal. The value of

HRWP can change only when DSR[HACT] = 0. HRWP is ignored when

the HI32 is not in a Universal Bus mode or double-strobe host port

mode is selected (DCTR[HM] ≠ $2 or $3, or HDSM = 0).

HDSM

Host Data Strobe Mode

Controls the data strobe mode of the host port pins in a Universal Bus

mode (DCTR[HM] = $2 or $3). When HDSM is cleared, the

double-strobe pin mode is selected: the HWR/HRW pin (HP29)

functions as host write strobe HWR, and HRD/HDS (HP30) functions as

a host read strobe HRD. When HDSM is set, the single-strobe pin mode

is selected: the HWR/HRW pin functions as host read/write HRW and

HRD/HDS functions as host data strobe

HDS.

The value of HDSM can

change only when DSR[HACT] = 0 in the DSR. HDSM is ignored when

the HI32 is not in a Universal Bus mode (DCTR[HM] ≠ $2 or $3).

12–7

Reserved. Write to 0 for future compatibility.

HINT

UB/PCI

Host Interrupt A

Controls the

HINTA

pin. When the core sets HINT, the

HINTA

pin is

driven low. When the core clears HINT, the HINTA pin is released.

Host Interface (HI32)

6-25

DSP56301 specifications

The Motorola DSP56301 is a highly efficient digital signal processor, specifically engineered for real-time audio and speech processing applications. This DSP is part of Motorola's renowned DSP56300 family, which is recognized for its innovative features and outstanding performance in the realm of digital signal processing.

One of the main features of the DSP56301 is its ability to handle complex computations at high speeds. With a maximum clock frequency of 66 MHz, it delivers fast performance, enabling it to process audio signals in real time. The chip is built on a 24-bit architecture, which allows for high-resolution audio processing. This is particularly beneficial in applications such as telecommunications, consumer audio devices, and professional audio equipment, where precision is paramount.

The DSP56301 boasts a comprehensive instruction set that includes efficient mathematical operations, which are essential for digital filters and audio effects processing. One of the key innovations of this device is its dual data path architecture, which permits simultaneous processing of multiple data streams. This feature significantly enhances the device's throughput and responsiveness, making it suitable for demanding applications such as voice recognition and synthesis.

In terms of memory regions, the DSP56301 includes several on-chip memory categories, such as program memory, data memory, and a specialized memory for coefficients. The architecture's support for external memory expansion further increases its versatility, allowing designers to tailor systems to their specific requirements.

The DSP56301 implements advanced features such as a powerful on-chip hardware multiplier and accumulator, simplifying complex mathematical tasks and accelerating the execution of algorithms. Its flexible interrupt system enhances its capability to respond to time-sensitive operations, while the integrated serial ports facilitate efficient data communication with external devices.

Power consumption is also a vital characteristic of the DSP56301. It is designed with energy efficiency in mind, allowing for extended operation in battery-powered devices. The chip’s low power requirements are particularly advantageous in portable audio devices and other applications where energy conservation is crucial.

In conclusion, the Motorola DSP56301 is an exceptional digital signal processor that combines high processing power, flexibility, and efficiency. Its main features, advanced technologies, and robust architecture make it a top choice for developers seeking to create sophisticated audio and signal processing systems. With its enduring legacy in the industry, the DSP56301 continues to be relevant in a variety of modern applications, ensuring it remains a valuable tool for engineers and designers.

Motorola DSP56301 Htap, Host Transfer Acknowledge Polarity, Host Read/Write Polarity, Hint UB/PCI

Models: DSP56301

Table 6-10.DSP Control Register (DCTR) Bit Definitions (Continued)

Mode

HTAP

Host Transfer Acknowledge Polarity

Host Read/Write Polarity

Host Data Strobe Mode

double-strobe pin mode is selected: the HWR/HRW pin (HP29)

HINT

UB/PCI

Host Interrupt A

HINTA

HINTA

Host Interface (HI32)

DSP56301 specifications