Host Interface (HI32)

Table 2-12.Host Port Pins (HI32) (Continued)

Signal

 

 

 

PCI

 

 

 

 

Universal Bus Mode

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Name

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Enhanced Universal Bus Mode

GPIO

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

HP22

HDEVSEL

 

 

 

 

 

 

 

 

 

 

 

HSAK

 

 

 

 

 

 

 

 

 

Host Device Select

 

Host Select Acknowledge

HI022

 

 

Sustained tri-state bidirectional pin.2

 

Active low output pin.

GPIO2

 

 

When actively driven, indicates the

 

Acknowledges to the host processor that the

 

 

 

driving device has decoded its

 

HI32 has identified its address as a slave.

 

 

 

address as a target of the current

 

HSAK is asserted when the HI32 is the

 

 

 

access. As an input it indicates

 

selected slave; otherwise HSAK is released.

 

 

 

whether any device on the bus is

 

 

 

 

 

 

 

 

 

 

 

 

selected.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

HP23

HLOCK

 

 

 

 

 

 

 

 

 

HIO23

 

HBS

 

 

 

 

 

 

 

 

Host Lock

 

Bus Strobe

GPIO2

 

 

Sustained tri-state bidirectional pin.2

 

Schmitt trigger input pin.

 

 

 

Indicates an atomic operation that

 

Asserted at the start of a bus cycle (for half of

 

 

 

may require multiple transactions to

 

a clock cycle) providing an “early bus start”

 

 

 

complete. When HLOCK is asserted,

 

signal. This enables the HI32 to respond

 

 

 

non-exclusive transactions to the

 

(HTA valid) earlier.

HBS

should be forced or

 

 

 

HI32 are ‘retried’ (that is, this is an

 

pulled up to VCC if not used (for example, ISA

 

 

 

entire resource lock).

 

bus).

 

 

 

 

 

 

 

 

 

 

 

HP24

HPAR

 

 

 

 

 

 

 

 

 

disconnected

 

HDAK

 

 

 

 

 

Host Parity

 

Host DMA Acknowledge

 

 

 

Tri-state bidirectional pin.

 

Schmitt trigger input pin.

 

 

 

Even parity across HAD[31–0] and

 

Indicates that the external DMA channel is

 

 

 

HC3/HBE3–HC0/HBE0. The master

 

accessing the HI32. The HI32 is selected as a

 

 

 

drives HPAR during address and write

 

DMA device if HDAK and HWR or HRD (in the

 

 

 

data phases; the target drives HPAR

 

double-strobe mode) or HDAK and HDS (in

 

 

 

during read data phases.

 

the single-strobe mode) are asserted. HDAK

 

 

 

 

 

 

 

should be forced or pulled up to VCC if not

 

 

 

 

 

 

 

used.

 

HP25

 

 

 

 

 

HDRQ

disconnected

 

HPERR

 

 

 

 

Parity Error

 

DMA Request

 

 

 

Sustained tri-state bidirectional pin.2

 

Output Pin.

 

 

 

Used for reporting of data parity

 

Supports ISA/EISA-type DMA data transfers.

 

 

 

errors. HPERR must be driven active

 

The HI32 asserts HDRQ when a DMA request

 

 

 

(by the agent receiving data) two

 

(receive and/or transmit) is generated in the

 

 

 

clocks following the data (that is one

 

HI32. HDRQ is deasserted when the DMA

 

 

 

clock following the HPAR signal)

 

request source is cleared

(HDAK

is asserted),

 

 

 

when a data parity error is detected.

 

masked (by RREQ=0 or TREQ=0) or disabled

 

 

 

 

 

 

 

(DMAE=0).

 

 

 

 

 

 

 

The polarity of HDRQ pin is controlled by

 

 

 

 

 

 

 

HDRP bit in the DCTR.

 

HP26

 

 

 

 

 

HAEN

disconnected

 

HGNT

 

 

 

 

Bus Grant

 

Host Address Enable

 

 

 

Input pin.

 

Input pin.

 

 

 

Indicates to the HI32 that it has

 

Enables ISA/EISA DMA / I/O type accesses.

 

 

 

mastership of the bus. If not used, this

 

When high, the HI32 responds to DMA cycles

 

 

 

pin should be forced or pulled up to

 

only (if DMAE=1 in the DCTR; if DMAE=0, the

 

 

 

Vcc.

 

HI32 ignores the access). When low, the HI32

 

 

 

 

 

 

 

responds when it identifies its address (that is

 

 

 

 

 

 

 

ISA/EISA DMA / I/O type-space accesses).

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2-18

DSP56301 User’s Manual

Page 48
Image 48
Motorola DSP56301 Host Device Select Host Select Acknowledge, Host Lock Bus Strobe, Host Parity Host DMA Acknowledge

DSP56301 specifications

The Motorola DSP56301 is a highly efficient digital signal processor, specifically engineered for real-time audio and speech processing applications. This DSP is part of Motorola's renowned DSP56300 family, which is recognized for its innovative features and outstanding performance in the realm of digital signal processing.

One of the main features of the DSP56301 is its ability to handle complex computations at high speeds. With a maximum clock frequency of 66 MHz, it delivers fast performance, enabling it to process audio signals in real time. The chip is built on a 24-bit architecture, which allows for high-resolution audio processing. This is particularly beneficial in applications such as telecommunications, consumer audio devices, and professional audio equipment, where precision is paramount.

The DSP56301 boasts a comprehensive instruction set that includes efficient mathematical operations, which are essential for digital filters and audio effects processing. One of the key innovations of this device is its dual data path architecture, which permits simultaneous processing of multiple data streams. This feature significantly enhances the device's throughput and responsiveness, making it suitable for demanding applications such as voice recognition and synthesis.

In terms of memory regions, the DSP56301 includes several on-chip memory categories, such as program memory, data memory, and a specialized memory for coefficients. The architecture's support for external memory expansion further increases its versatility, allowing designers to tailor systems to their specific requirements.

The DSP56301 implements advanced features such as a powerful on-chip hardware multiplier and accumulator, simplifying complex mathematical tasks and accelerating the execution of algorithms. Its flexible interrupt system enhances its capability to respond to time-sensitive operations, while the integrated serial ports facilitate efficient data communication with external devices.

Power consumption is also a vital characteristic of the DSP56301. It is designed with energy efficiency in mind, allowing for extended operation in battery-powered devices. The chip’s low power requirements are particularly advantageous in portable audio devices and other applications where energy conservation is crucial.

In conclusion, the Motorola DSP56301 is an exceptional digital signal processor that combines high processing power, flexibility, and efficiency. Its main features, advanced technologies, and robust architecture make it a top choice for developers seeking to create sophisticated audio and signal processing systems. With its enduring legacy in the industry, the DSP56301 continues to be relevant in a variety of modern applications, ensuring it remains a valuable tool for engineers and designers.