DSP PCI Master Control Register Dpmc, BL4

HI32 DSP-Side Programming Model

Table 6-11.DSP PCI Control Register (DPCR) Bit Definitions (Continued)

Bit Number	Bit Name	Reset Value	Description

4	MAIE	0	Master Address Interrupt Enable
			Enables/disables a DSP56300 core interrupt request when the HI32 is
			not the PCI transaction initiator in the PCI mode (DCTR[HM] = $1). If
			MAIE is cleared, master address interrupt requests are disabled. If
			MAIE is set, a master address interrupt request is generated if the
			master address request (MARQ) status bit in the DPSR is set.

3		0	Reserved. Write to 0 for future compatibility.

2	MRIE	0	Master Receive Interrupt Enable
			Enables/disables a DSP56300 core interrupt request when the master
			receive data request (MRRQ) status bit in the DSP Status Register
			(DPSR) is set. If MRIE is cleared, master receive data interrupt
			requests are disabled.

1	MTIE	o	Master Transmit Interrupt Enable
			Enables/disables a DSP56300 core interrupt request when the master
			transmit data request (MTRQ) status bit in the DPSR is set. If MTIE is
			cleared, MTRQ interrupt requests are disabled.

0		0	Reserved. Write to 0 for future compatibility.

6.7.3DSP PCI Master Control Register (DPMC)

The DPMC is a 24-bit read/write register by which the DSP56300 core generates the two most significant bytes of the 32-bit PCI transaction address and controls the burst length and data transfer format. The host processor cannot access the DPMC. The DPMC bits are ignored when the HI32 is not in PCI mode (DCTR[HM]≠$1). The DPMC can be written only if MARQ is set or in Self-Configuration mode.

23	22	21	20	19	18	17	16

FC1	FC0	BL5	BL4	BL3	BL2	BL1	BL0

15	14	13	12	11	10	9	8

AR31	AR30	AR29	AR28	AR27	AR26	AR25	AR24

7	6	5	4	3	2	1	0

AR23	AR22	AR21	AR20	AR19	AR18	AR17	AR16

Figure 6-7.DSP PCI Master Control Register (DPMC)

6-30	DSP56301 User’s Manual

DSP56301 specifications

The Motorola DSP56301 is a highly efficient digital signal processor, specifically engineered for real-time audio and speech processing applications. This DSP is part of Motorola's renowned DSP56300 family, which is recognized for its innovative features and outstanding performance in the realm of digital signal processing.

One of the main features of the DSP56301 is its ability to handle complex computations at high speeds. With a maximum clock frequency of 66 MHz, it delivers fast performance, enabling it to process audio signals in real time. The chip is built on a 24-bit architecture, which allows for high-resolution audio processing. This is particularly beneficial in applications such as telecommunications, consumer audio devices, and professional audio equipment, where precision is paramount.

The DSP56301 boasts a comprehensive instruction set that includes efficient mathematical operations, which are essential for digital filters and audio effects processing. One of the key innovations of this device is its dual data path architecture, which permits simultaneous processing of multiple data streams. This feature significantly enhances the device's throughput and responsiveness, making it suitable for demanding applications such as voice recognition and synthesis.

In terms of memory regions, the DSP56301 includes several on-chip memory categories, such as program memory, data memory, and a specialized memory for coefficients. The architecture's support for external memory expansion further increases its versatility, allowing designers to tailor systems to their specific requirements.

The DSP56301 implements advanced features such as a powerful on-chip hardware multiplier and accumulator, simplifying complex mathematical tasks and accelerating the execution of algorithms. Its flexible interrupt system enhances its capability to respond to time-sensitive operations, while the integrated serial ports facilitate efficient data communication with external devices.

Power consumption is also a vital characteristic of the DSP56301. It is designed with energy efficiency in mind, allowing for extended operation in battery-powered devices. The chip’s low power requirements are particularly advantageous in portable audio devices and other applications where energy conservation is crucial.

In conclusion, the Motorola DSP56301 is an exceptional digital signal processor that combines high processing power, flexibility, and efficiency. Its main features, advanced technologies, and robust architecture make it a top choice for developers seeking to create sophisticated audio and signal processing systems. With its enduring legacy in the industry, the DSP56301 continues to be relevant in a variety of modern applications, ensuring it remains a valuable tool for engineers and designers.

Motorola DSP56301 user manual DSP PCI Master Control Register Dpmc, BL4, BL1 BL0

Models: DSP56301

Table 6-11.DSP PCI Control Register (DPCR) Bit Definitions (Continued)

Master Address Interrupt Enable

Master Receive Interrupt Enable

Master Transmit Interrupt Enable

6.7.3DSP PCI Master Control Register (DPMC)

BL4

BL1

BL0

Figure 6-7.DSP PCI Master Control Register (DPMC)

DSP56301 specifications