HI32 Programming Model/Quick Reference

6.9HI32 Programming Model/Quick Reference

HI32 Registers—Quick Reference

Reg

Bit

Num

Mnemonic

Name

Val

Function

 

 

 

 

 

Comments

Reset Type

HS PH PS

DSP SIDE

DCTR

0

HCIE

Host Command

0

HCP interrupt disabled

 

0

-

-

 

 

Interrupt Enable

1

HCP interrupt enabled

 

 

 

 

 

 

 

 

 

1

STIE

Slave Transmit

0

STRQ interrupt disabled

 

0

-

-

 

 

Interrupt Enable

1

STRQ interrupt enabled

 

 

 

 

 

 

 

 

 

2

SRIE

Slave Receive

0

SRRQ interrupt disabled

 

0

-

-

 

 

Interrupt Enable

1

SRRQ interrupt enabled

 

 

 

 

 

 

 

 

 

5-3

HF[5–3]

Host Flags

 

 

 

 

 

 

general-purpose

$0

-

-

 

 

 

 

 

 

 

 

 

flags

 

 

 

 

 

 

 

 

 

 

 

 

 

 

6

HINT

Host Interrupt A

0

HINTA pin is high impedance

 

0

 

 

 

 

 

1

HINTA pin is driven low

 

 

 

 

 

 

 

 

 

 

 

 

 

HDSM

Host Data Strobe

0

 

+

 

(double data

changed only in

 

 

 

 

 

HWR

HRD

 

 

 

 

13

 

Mode

1

strobe)

 

 

PS reset;

0

-

-

 

 

 

 

HRW + HDS (single data

ignored when

 

 

 

 

 

 

 

 

 

 

 

 

 

strobe)

not in UBM

 

 

 

 

 

HRWP

Host RD/WR Polarity

0

HRW (0 = WRITE, 1 = READ)

changed only in

 

 

 

 

14

 

 

1

HRW(0 = READ, 1 = WRITE)

PS reset;

0

-

-

 

 

 

 

 

 

 

 

 

ignored when

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

not in UBM

 

 

 

 

 

HTAP

Host Transfer

0

HTA

changed only in

 

 

 

 

15

 

Acknowledge Polarity

1

HTA

PS reset;ignored

0

-

-

 

 

 

 

 

 

 

 

 

when not in

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

UBM

 

 

 

 

 

HDRP

Host DMA Request

0

HDRQ

changed only in

 

 

 

 

16

 

Polarity

1

HDRQ

PS reset;ignored

0

-

-

 

 

 

 

 

 

 

 

 

when not in

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

UBM

 

 

 

 

 

HRSP

Host Reset Polarity

0

HRST

changed only in

 

 

 

 

17

 

 

1

HRST

PS reset;ignored

0

-

-

 

 

 

 

 

 

 

 

 

when not in

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

UBM

 

 

 

 

 

HIRH

Host Interrupt Request

0

 

 

pulsed

changed only in

 

 

 

 

 

HIRQ

 

 

 

 

 

 

Handshake Mode

1

HIRQ = full handshake

PS reset

 

 

 

 

 

 

 

 

 

 

 

 

 

HIRQ pulse

 

 

 

 

18

 

 

 

 

 

 

 

 

width is defined

0

-

-

 

 

 

 

 

 

 

 

 

 

by CLAT;

 

 

 

 

 

 

 

 

 

 

 

 

 

ignored when

 

 

 

 

 

 

 

 

 

 

 

 

 

not in UBM

 

 

 

 

 

HIRD

Host Interrupt Request

0

 

 

= open drain

changed only in

 

 

 

 

 

HIRQ

 

 

 

 

19

 

Drive Control

1

HIRQ = driven

PS reset;

0

-

-

 

 

 

 

 

 

 

 

 

ignored when

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

not in UBM

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

6-74

DSP56301 User’s Manual

Page 191 Page 193
Page 192
Image 192
Motorola DSP56301 user manual HI32 Programming Model/Quick Reference, Hs Ph Ps, Dctr Hcie, UBM Hrsp, UBM Hirh
Page 191 Page 193

DSP56301 specifications

The Motorola DSP56301 is a highly efficient digital signal processor, specifically engineered for real-time audio and speech processing applications. This DSP is part of Motorola's renowned DSP56300 family, which is recognized for its innovative features and outstanding performance in the realm of digital signal processing.

One of the main features of the DSP56301 is its ability to handle complex computations at high speeds. With a maximum clock frequency of 66 MHz, it delivers fast performance, enabling it to process audio signals in real time. The chip is built on a 24-bit architecture, which allows for high-resolution audio processing. This is particularly beneficial in applications such as telecommunications, consumer audio devices, and professional audio equipment, where precision is paramount.

The DSP56301 boasts a comprehensive instruction set that includes efficient mathematical operations, which are essential for digital filters and audio effects processing. One of the key innovations of this device is its dual data path architecture, which permits simultaneous processing of multiple data streams. This feature significantly enhances the device's throughput and responsiveness, making it suitable for demanding applications such as voice recognition and synthesis.

In terms of memory regions, the DSP56301 includes several on-chip memory categories, such as program memory, data memory, and a specialized memory for coefficients. The architecture's support for external memory expansion further increases its versatility, allowing designers to tailor systems to their specific requirements.

The DSP56301 implements advanced features such as a powerful on-chip hardware multiplier and accumulator, simplifying complex mathematical tasks and accelerating the execution of algorithms. Its flexible interrupt system enhances its capability to respond to time-sensitive operations, while the integrated serial ports facilitate efficient data communication with external devices.

Power consumption is also a vital characteristic of the DSP56301. It is designed with energy efficiency in mind, allowing for extended operation in battery-powered devices. The chip’s low power requirements are particularly advantageous in portable audio devices and other applications where energy conservation is crucial.

In conclusion, the Motorola DSP56301 is an exceptional digital signal processor that combines high processing power, flexibility, and efficiency. Its main features, advanced technologies, and robust architecture make it a top choice for developers seeking to create sophisticated audio and signal processing systems. With its enduring legacy in the industry, the DSP56301 continues to be relevant in a variety of modern applications, ensuring it remains a valuable tool for engineers and designers.
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