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Motorola DSP56301 user manual Host Receive Data Transfer Format

Models: DSP56301

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Host-Side Programming Model

Table 6-22.Host Interface Control Register (HCTR) Bit Definitions (Continued)

Bit

Bit Name

Reset

Mode

Description

Number

Value

 

 

 

 

 

 

 

 

 

 

 

 

 

13

 

0

 

Reserved. Write to zero for future compatibility.

 

 

 

 

 

12–11

HRF[1–0]

0

UBM

Host Receive Data Transfer Format

 

 

 

PCI

Define data transfer formats for DSP-to-host communication. The data

 

 

 

 

transfer format converter (HDTFC) operates according to the specified

 

 

 

 

HRF[1–0] (See Table 6-5,Receive Transfer Data Formats, on

 

 

 

 

page 6-10). The personal hardware reset clears HRF[1–0].

 

 

 

 

DSP-to-PCI host data transfer formats (DCTR[HM] = $1):

 

 

 

 

ν If HCTR[HRF] = $0 (32-bit data mode):

 

 

 

 

The two least significant bytes of two words written to the DTXS

 

 

 

 

are transferred to the HRXS. The two least significant bytes of the

 

 

 

 

first word written to the DTXS are transferred to the two least

 

 

 

 

significant bytes of the HRXS. The two least significant bytes of the

 

 

 

 

second word written to the DTXS are transferred to the two most

 

 

 

 

significant bytes of the HRXS. All four HRXS bytes are output to

 

 

 

 

the HAD[31–0] pins.

 

 

 

 

ν If HCTR[HRF] = $1:

 

 

 

 

The data written to the DTXS is transferred to the three least

 

 

 

 

significant HRXS bytes and output to the HAD[31–0] pins as right

 

 

 

 

aligned and zero extended in the most significant byte.

 

 

 

 

ν If HCTR[HRF] = $2:

 

 

 

 

The data written to the DTXS is transferred to the three least

 

 

 

 

significant HRXS bytes and output to the HAD[31–0] pins as left

 

 

 

 

aligned and zero filled in the least significant byte.

 

 

 

 

ν If HCTR[HRF] = $3:

 

 

 

 

The data written to the DTXS is transferred to the three least

 

 

 

 

significant HRXS bytes and output to the HAD[31–0] pins as right

 

 

 

 

aligned and sign extended in the most significant byte.

Universal Bus mode DSP-to-host data transfer formats (DCTR[HM] = $2 or $3):

νIf HCTR[HRF] = $0:

The data written to the DTXS is transferred to the HRXS and output to the HI32 data pins HD[23–0].

νIf HCTR[HRF] = $1 or $2:

The two least significant bytes of the data written to the DTXS is transferred to the HRXS and output to HI32 data pins HD[15–0].

νIf HCTR[HRF] = $3:

The two most significant bytes of the data written to the DTXS is transferred to the HRXS and output to HI32 data pins HD[15–0].

To assure proper operation, HRF[1–0] can be changed only if the DSP-to-host slave data path is empty. In addition, switching between 32-bit data modes and non-32-bit data modes can occur only in the personal software reset state (DCTR[HM] = $0 and DSR[HACT] = 0).

10

 

0

 

Reserved. Write to zero for future compatibility.

 

 

 

 

 

6-50

DSP56301 User’s Manual

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Motorola DSP56301 user manual Host Receive Data Transfer Format
Page 167 Page 169

DSP56301 specifications

The Motorola DSP56301 is a highly efficient digital signal processor, specifically engineered for real-time audio and speech processing applications. This DSP is part of Motorola's renowned DSP56300 family, which is recognized for its innovative features and outstanding performance in the realm of digital signal processing.

One of the main features of the DSP56301 is its ability to handle complex computations at high speeds. With a maximum clock frequency of 66 MHz, it delivers fast performance, enabling it to process audio signals in real time. The chip is built on a 24-bit architecture, which allows for high-resolution audio processing. This is particularly beneficial in applications such as telecommunications, consumer audio devices, and professional audio equipment, where precision is paramount.

The DSP56301 boasts a comprehensive instruction set that includes efficient mathematical operations, which are essential for digital filters and audio effects processing. One of the key innovations of this device is its dual data path architecture, which permits simultaneous processing of multiple data streams. This feature significantly enhances the device's throughput and responsiveness, making it suitable for demanding applications such as voice recognition and synthesis.

In terms of memory regions, the DSP56301 includes several on-chip memory categories, such as program memory, data memory, and a specialized memory for coefficients. The architecture's support for external memory expansion further increases its versatility, allowing designers to tailor systems to their specific requirements.

The DSP56301 implements advanced features such as a powerful on-chip hardware multiplier and accumulator, simplifying complex mathematical tasks and accelerating the execution of algorithms. Its flexible interrupt system enhances its capability to respond to time-sensitive operations, while the integrated serial ports facilitate efficient data communication with external devices.

Power consumption is also a vital characteristic of the DSP56301. It is designed with energy efficiency in mind, allowing for extended operation in battery-powered devices. The chip’s low power requirements are particularly advantageous in portable audio devices and other applications where energy conservation is crucial.

In conclusion, the Motorola DSP56301 is an exceptional digital signal processor that combines high processing power, flexibility, and efficiency. Its main features, advanced technologies, and robust architecture make it a top choice for developers seeking to create sophisticated audio and signal processing systems. With its enduring legacy in the industry, the DSP56301 continues to be relevant in a variety of modern applications, ensuring it remains a valuable tool for engineers and designers.