Programming Sheets

Application:

 

Date:

Programmer:

Sheet 1 of 2

 

SCI

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Transmitter Enable

 

 

 

 

 

Word Select Bits

 

 

 

 

 

 

 

 

0

= Transmitter Disable

 

 

 

 

 

0 0 0

= 8-bit Synchronous Data (Shift Register Mode)

 

 

1

= Transmitter Enable

 

 

 

 

 

0 0 1

= Reserved

 

 

 

 

 

 

 

 

Idle Line Interrupt Enable

 

 

 

 

 

0 1 0

= 10-bit Asynchronous (1 Start, 8 Data, 1 Stop)

 

 

 

 

 

 

 

0 1 1

= Reserved

 

 

 

 

 

 

 

 

0

= Idle Line Interrupt Disabled

 

 

 

 

1 0 0

= 11-bit Asynchronous (1 Start, 8 Data, Even Parity, 1 Stop)

1

= Idle Line Interrupt Enabled

 

 

 

 

 

 

 

 

1 0 1

= 11-bit Asynchronous (1 Start, 8 Data, Odd Parity, 1 Stop)

 

 

 

 

 

 

 

Receive Interrupt Enable

 

 

 

 

 

1 1 0

= 11-bit Multidrop (1 Start, 8 Data, Data Type, 1 Stop)

 

 

 

 

 

 

1 1 1

= Reserved

 

 

 

 

 

 

 

 

0

= Receive Interrupt Disabled

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

= Idle Line Interrupt Enabled

 

 

 

 

 

Receiver Wakeup Enable

 

SCI Shift Direction

 

 

 

 

 

 

 

 

 

 

 

Transmit Interrupt Enable

 

 

 

 

 

 

0 = receiver has awakened

 

0 = LSB First

 

 

0

= Transmit Interrupts Disabled

 

 

 

 

 

1 = Wakeup function enabled

 

1 = MSB First

 

 

1

= Transmit Interrupts Enabled

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Timer Interrupt Enable

 

 

 

 

 

Wired-Or Mode Select

 

Send Break

 

 

 

 

 

 

 

 

1 = Multidrop

 

 

 

0 = Send break, then revert

 

0

= Timer Interrupts Disabled

 

 

 

 

0 = Point to Point

 

 

1 = Continually send breaks

 

1

= Timer Interrupts Enabled

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SCI Timer Interrupt Rate

 

 

 

 

Receiver Enable

 

 

Wakeup Mode Select

 

 

 

 

 

 

0 = Receiver Disabled

 

 

 

 

 

 

 

 

0 = Idle Line Wakeup

 

 

0

= ÷ 32, 1 = ÷ 1

 

 

 

 

1 = Receiver Enabled

 

 

1 = Address Bit Wakeup

 

 

SCI Clock Polarity

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

= Clock Polarity is Positive

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

= Clock Polarity is Negative

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SCI Receive Exception Inerrupt

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

= Receive Interrupt Disable

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

= Receive Interrupt Enable

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

23

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

*0

REIE

SCKP STIR

TMIE

TIE

RIE

ILIE

TE

RE

WOMS RWU

WAKE SBK SSFTD WDS2 WDS1 WDS0

 

SCI Control Register (SCR)

 

X:$FFFF9C Read/Write

 

 

 

 

 

Reset $000000

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

*= Reserved, Program as 0

Figure B-23.SCI Control Register (SCR)

Programming Reference

B-35

Page 346 Page 348
Page 347
Image 347
Motorola DSP56301 user manual SCI Control Register SCR $FFFF9C Read/Write
Page 346 Page 348

DSP56301 specifications

The Motorola DSP56301 is a highly efficient digital signal processor, specifically engineered for real-time audio and speech processing applications. This DSP is part of Motorola's renowned DSP56300 family, which is recognized for its innovative features and outstanding performance in the realm of digital signal processing.

One of the main features of the DSP56301 is its ability to handle complex computations at high speeds. With a maximum clock frequency of 66 MHz, it delivers fast performance, enabling it to process audio signals in real time. The chip is built on a 24-bit architecture, which allows for high-resolution audio processing. This is particularly beneficial in applications such as telecommunications, consumer audio devices, and professional audio equipment, where precision is paramount.

The DSP56301 boasts a comprehensive instruction set that includes efficient mathematical operations, which are essential for digital filters and audio effects processing. One of the key innovations of this device is its dual data path architecture, which permits simultaneous processing of multiple data streams. This feature significantly enhances the device's throughput and responsiveness, making it suitable for demanding applications such as voice recognition and synthesis.

In terms of memory regions, the DSP56301 includes several on-chip memory categories, such as program memory, data memory, and a specialized memory for coefficients. The architecture's support for external memory expansion further increases its versatility, allowing designers to tailor systems to their specific requirements.

The DSP56301 implements advanced features such as a powerful on-chip hardware multiplier and accumulator, simplifying complex mathematical tasks and accelerating the execution of algorithms. Its flexible interrupt system enhances its capability to respond to time-sensitive operations, while the integrated serial ports facilitate efficient data communication with external devices.

Power consumption is also a vital characteristic of the DSP56301. It is designed with energy efficiency in mind, allowing for extended operation in battery-powered devices. The chip’s low power requirements are particularly advantageous in portable audio devices and other applications where energy conservation is crucial.

In conclusion, the Motorola DSP56301 is an exceptional digital signal processor that combines high processing power, flexibility, and efficiency. Its main features, advanced technologies, and robust architecture make it a top choice for developers seeking to create sophisticated audio and signal processing systems. With its enduring legacy in the industry, the DSP56301 continues to be relevant in a variety of modern applications, ensuring it remains a valuable tool for engineers and designers.
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