Host Bus Clock

Host Interface (HI32)

Table 2-12.Host Port Pins (HI32) (Continued)

Signal	PCI	Universal Bus Mode
Signal
Name
		Enhanced Universal Bus Mode	GPIO




HP32	HCLK	Reserved.	disconnected
	Host Bus Clock	Must be forced or pulled up to VCC.
	Input pin.
	Provides timing for all transactions on
	PCI. All other PCI signals are
	sampled on the HCLK rising edge.
HP[40–33]	HAD[31–16]	HD[23–8]	disconnected
	Address/Data Multiplexed Bus	Data Bus
	Tri-state bidirectional bus.	Tri-state bidirectional bus.
	During the first clock of a transaction	Transfers data between the host processor
	HAD[31–16] contain the physical byte	and the HI32. This bus is released
	address (32 bits). During subsequent	(disconnected) when the HI32 is not selected
	clock HAD[31–16] contain data.	by HA[10–0]. The HD[23–0] pins are driven by
		the HI32 during a read access, and are inputs
		to the HI32 during a write access.
		During operation with a host bus less than 16
		bits wide, the HD[23–8] pins not used to
		transfer data must be pulled to Vcc or GND.
		For example: during operation with an 8-bit
		bus, HP[40–33] must be pulled up to Vcc or
		pulled down to GND.
		Note: Motorola recommends that you pull
		these unused data lines down. Pulling these
		lines up sets the corresponding bits when the
		external host writes to the HCTR.
HP[48–41]		HD[23–16]	disconnected
		Data Bus
		Tri-state bidirectional bus.
		Transfers data between the host processor
		and the HI32.
		This bus is released (disconnected) when the
		HI32 is not selected by HA[10–0]. The
		HD[23–16] pins are driven by the HI32 during
		a read access and are inputs to the HI32
		during a write access.
		HD[23–16] outputs are high impedance if
		HRF≠$0. HD[23–16] inputs are disconnected
		if HTF≠$0.
		During operation with a host bus less than 24
		bits wide, the data pins not used to transfer
		data must be forced or pulled to Vcc or to
		GND. For example: during operations with a
		16-bit bus (for example, ISA bus), HP[48–41]
		must be forced or pulled up to VCC or pulled
		down to GND.
		Note: Motorola recommends that you pull
		these unused data lines down. Pulling the
		lines up sets the corresponding bits when the
		external host writes to the HCTR.

Signals/Connections

2-21

DSP56301 specifications

The Motorola DSP56301 is a highly efficient digital signal processor, specifically engineered for real-time audio and speech processing applications. This DSP is part of Motorola's renowned DSP56300 family, which is recognized for its innovative features and outstanding performance in the realm of digital signal processing.

One of the main features of the DSP56301 is its ability to handle complex computations at high speeds. With a maximum clock frequency of 66 MHz, it delivers fast performance, enabling it to process audio signals in real time. The chip is built on a 24-bit architecture, which allows for high-resolution audio processing. This is particularly beneficial in applications such as telecommunications, consumer audio devices, and professional audio equipment, where precision is paramount.

The DSP56301 boasts a comprehensive instruction set that includes efficient mathematical operations, which are essential for digital filters and audio effects processing. One of the key innovations of this device is its dual data path architecture, which permits simultaneous processing of multiple data streams. This feature significantly enhances the device's throughput and responsiveness, making it suitable for demanding applications such as voice recognition and synthesis.

In terms of memory regions, the DSP56301 includes several on-chip memory categories, such as program memory, data memory, and a specialized memory for coefficients. The architecture's support for external memory expansion further increases its versatility, allowing designers to tailor systems to their specific requirements.

The DSP56301 implements advanced features such as a powerful on-chip hardware multiplier and accumulator, simplifying complex mathematical tasks and accelerating the execution of algorithms. Its flexible interrupt system enhances its capability to respond to time-sensitive operations, while the integrated serial ports facilitate efficient data communication with external devices.

Power consumption is also a vital characteristic of the DSP56301. It is designed with energy efficiency in mind, allowing for extended operation in battery-powered devices. The chip’s low power requirements are particularly advantageous in portable audio devices and other applications where energy conservation is crucial.

In conclusion, the Motorola DSP56301 is an exceptional digital signal processor that combines high processing power, flexibility, and efficiency. Its main features, advanced technologies, and robust architecture make it a top choice for developers seeking to create sophisticated audio and signal processing systems. With its enduring legacy in the industry, the DSP56301 continues to be relevant in a variety of modern applications, ensuring it remains a valuable tool for engineers and designers.

Motorola DSP56301 user manual Host Bus Clock, Address/Data Multiplexed Bus Data Bus

Models: DSP56301

Table 2-12.Host Port Pins (HI32) (Continued)

PCI

GPIO

HCLK

Reserved.

Address/Data Multiplexed Bus

Data Bus

DSP56301 specifications