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Motorola DSP56301 user manual Gpio Mode Dctrhm = $4, Self-Configuration Mode Dctrhm = $5

Models: DSP56301

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DSP-Side Operating Modes

In addition, for Universal Bus mode, pins HP[22–20] are GPI/O. For Enhanced Universal Bus mode, two control signals (data direction and data output enable) are output to an optional external data buffer. Also, there is host select acknowledge output.

6.5.4 GPIO Mode (DCTR[HM] = $4)

ν

ν

General-purpose I/O (GPIO) port, pins HP[23–0].

Pins HP[48–33], HP[30–24] are disconnected.

νHP31 and HP32 are unused and must be forced or pulled up to VCC.

νMinimum current consumption.

6.5.5Self-Configuration Mode (DCTR[HM] = $5)

νIndirect write-only DSP56300 core access to to all registers in the PCI configuration space except CDID/CVID.

νAll host port pins are in the disconnected state.

In Self-Configuration mode, the HI32 base address and HIRQ pulse width are programmed for operation in the Universal Bus mode, and the configuration registers are prorammed for operation in a PCI environment without an external system configurator.

In Self-Configuration mode (DCTR[HM] = $5), the DSP56300 core can indirectly write to all the writeable HI32 configuration registers. The DSP56300 core writes the 32-bit data to the AR bits of the DPMC and DPAR registers (the remaining bits in these registers are ignored). The two most significant bytes of the 32 bits are written to the DPMC, the two least significant, to the DPAR. Therefore, the 16 most significant bits of the 32 bit PCI data word reside in the DPMC AR bits (16 least significant bits of DPMC). The 16 least significant bits of the 32-bit PCI data word reside in the DPAR AR bits (16 least significant bits of DPAR). The HI32 hardware transfers the data to the configuration register. The registers must be written sequentially beginning with the CSTR/CCMR register (location $04). After each write to the DPAR, a 32-bit data word (Dword) is transferred to the accessed register, and an internal pointer advances to point to the next Dword location in the configuration space.

Note: At least one DSP instruction must appear between writing the Self-Configuration mode (HM[2–0] = $5) and the first write to the DPAR if the first write requires one DSP clock cycle (for example, move immediate and move from external memory require more than one clock cycle).

If the SIDR/SVID register is to be written in Self-Configuration mode and the host has already written the CBMA address, this address is over written by this prodcedure. You must be careful to ensure that this does not happen. In the example code that follows, the DPMC AR bits are loaded with the Base Address upper 16 bits of the 32 bit PCI word (Dword) and

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DSP56301 User’s Manual

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Page 134
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Motorola DSP56301 user manual Gpio Mode Dctrhm = $4, Self-Configuration Mode Dctrhm = $5
Page 133 Page 135

DSP56301 specifications

The Motorola DSP56301 is a highly efficient digital signal processor, specifically engineered for real-time audio and speech processing applications. This DSP is part of Motorola's renowned DSP56300 family, which is recognized for its innovative features and outstanding performance in the realm of digital signal processing.

One of the main features of the DSP56301 is its ability to handle complex computations at high speeds. With a maximum clock frequency of 66 MHz, it delivers fast performance, enabling it to process audio signals in real time. The chip is built on a 24-bit architecture, which allows for high-resolution audio processing. This is particularly beneficial in applications such as telecommunications, consumer audio devices, and professional audio equipment, where precision is paramount.

The DSP56301 boasts a comprehensive instruction set that includes efficient mathematical operations, which are essential for digital filters and audio effects processing. One of the key innovations of this device is its dual data path architecture, which permits simultaneous processing of multiple data streams. This feature significantly enhances the device's throughput and responsiveness, making it suitable for demanding applications such as voice recognition and synthesis.

In terms of memory regions, the DSP56301 includes several on-chip memory categories, such as program memory, data memory, and a specialized memory for coefficients. The architecture's support for external memory expansion further increases its versatility, allowing designers to tailor systems to their specific requirements.

The DSP56301 implements advanced features such as a powerful on-chip hardware multiplier and accumulator, simplifying complex mathematical tasks and accelerating the execution of algorithms. Its flexible interrupt system enhances its capability to respond to time-sensitive operations, while the integrated serial ports facilitate efficient data communication with external devices.

Power consumption is also a vital characteristic of the DSP56301. It is designed with energy efficiency in mind, allowing for extended operation in battery-powered devices. The chip’s low power requirements are particularly advantageous in portable audio devices and other applications where energy conservation is crucial.

In conclusion, the Motorola DSP56301 is an exceptional digital signal processor that combines high processing power, flexibility, and efficiency. Its main features, advanced technologies, and robust architecture make it a top choice for developers seeking to create sophisticated audio and signal processing systems. With its enduring legacy in the industry, the DSP56301 continues to be relevant in a variety of modern applications, ensuring it remains a valuable tool for engineers and designers.