Core Configuration

Chapter 4

This chapter presents DSP56300 core configuration details specific to the DSP56301. These configuration details include the following:

νOperating modes

νBootstrap program

νCentral Processor registers

—Status Register (SR)

—Operating Mode Register (OMR)

νInterrupt Priority Registers (IPRC and IPRP)

νPLL Control (PCTL) register

νBus Interface Unit registers

—Bus Control Register (BCR)

—DRAM Control Register (DCR)

—Address Attribute Registers (AAR[3–0])

νDMA Control Registers 5–0 (DCR[5–0])

νDevice Identification Register (IDR)

νJTAG Identification (ID) Register

νJTAG Boundary Scan Register (BSR)

For information about specific registers or modules in the DSP56300 core, refer to the DSP56300 Family Manual.

Core Configuration

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Motorola DSP56301 user manual Core Configuration

DSP56301 specifications

The Motorola DSP56301 is a highly efficient digital signal processor, specifically engineered for real-time audio and speech processing applications. This DSP is part of Motorola's renowned DSP56300 family, which is recognized for its innovative features and outstanding performance in the realm of digital signal processing.

One of the main features of the DSP56301 is its ability to handle complex computations at high speeds. With a maximum clock frequency of 66 MHz, it delivers fast performance, enabling it to process audio signals in real time. The chip is built on a 24-bit architecture, which allows for high-resolution audio processing. This is particularly beneficial in applications such as telecommunications, consumer audio devices, and professional audio equipment, where precision is paramount.

The DSP56301 boasts a comprehensive instruction set that includes efficient mathematical operations, which are essential for digital filters and audio effects processing. One of the key innovations of this device is its dual data path architecture, which permits simultaneous processing of multiple data streams. This feature significantly enhances the device's throughput and responsiveness, making it suitable for demanding applications such as voice recognition and synthesis.

In terms of memory regions, the DSP56301 includes several on-chip memory categories, such as program memory, data memory, and a specialized memory for coefficients. The architecture's support for external memory expansion further increases its versatility, allowing designers to tailor systems to their specific requirements.

The DSP56301 implements advanced features such as a powerful on-chip hardware multiplier and accumulator, simplifying complex mathematical tasks and accelerating the execution of algorithms. Its flexible interrupt system enhances its capability to respond to time-sensitive operations, while the integrated serial ports facilitate efficient data communication with external devices.

Power consumption is also a vital characteristic of the DSP56301. It is designed with energy efficiency in mind, allowing for extended operation in battery-powered devices. The chip’s low power requirements are particularly advantageous in portable audio devices and other applications where energy conservation is crucial.

In conclusion, the Motorola DSP56301 is an exceptional digital signal processor that combines high processing power, flexibility, and efficiency. Its main features, advanced technologies, and robust architecture make it a top choice for developers seeking to create sophisticated audio and signal processing systems. With its enduring legacy in the industry, the DSP56301 continues to be relevant in a variety of modern applications, ensuring it remains a valuable tool for engineers and designers.

Contents

Revision 3, March DSP56301 User’s Manual ASIA/PACIFIC How to reach usUSA/EUROPE JapanPage Page Contents Chapter Core Configuration Chapter Memory Configuration Chapter Host Interface HI32 Chapter Programming the Peripherals Chapter Enhanced Synchronous Serial Interface Essi Chapter Serial Communication Interface SCI Chapter Triple Timer Module Chapter a Bootstrap Program Chapter B Programming ReferenceIndex DSP56301 User’s Manual Figures Xii Pulse Width Modulation Toggle Mode, TRM = DSP Control Register Dctr DSP PCI Control Register Dpcr Tables Tables Essi Clock Sources Overview Manual Organization Ground2 High True/Low True Signal ConventionsSignal/Symbol Logic State Signal State Voltage Manual Conventions PIN is a generic term for any pin on the chip Ground DSP56300 Core Features Program RAM Instruction Data RAM Switch Size Cache Size CE = MS =Size Cache Data ALU DSP56300 Core Functional Blocks Address Generation Unit AGU Data ALU RegistersMultiplier-Accumulator MAC Program Control Unit PCU Jtag TAP and OnCE Module PLL and Clock Oscillator DSP56301 Switch Memory Configuration Internal BusesOn-Chip Memory DMA Memory Expansion AreaExpansion Area Enhance Synchronous Serial Interface Essi General-Purpose Input/Output Gpio signalsPeripherals Host Interface HI32 Serial Communications Interface SCI Triple Timer Module DSP56300FM/AD Related Documents and Web SitesDSP56301 Documentation Name Description Order Number ESSI1 DSP56301 Functional Signal GroupingsTimers JTAG/OnCE Port Enhanced Synchronous Serial Interfaces ESSI0 See -2for a listing of the Host Interface/Port B Signals DSP56301Port a Host Interface/Port B Detail Signal Diagram Ground PowerPower Inputs Ground Signals PLL Clock SignalsPhase-Lock Loop Signals Clock External Bus Control External Memory Expansion Port Port aExternal Address Bus External Data Bus Output Tri-stated Is asserted for half a clock Signals are tri-statedArbitration is reset to the bus slave state Output Tri-stated Is an active-low output that is Bclk CAS Nonmaskable Interrupt-After Interrupt and Mode ControlInterrupt and Mode Control Signal State Type During Signal Description Name 10.Host Interface Host Interface HI32 Command 0-3/Byte Enable 0-3 -When the HI32 is programmed Hperr HBSHpar Hdak HWR HserrHirq Hstop Signal PCI Mode Enhanced Universal Bus Mode Gpio Mode Name 11.Summary of HI32 Signals and Modes HAD12 HD4 HIO12 HP8 HAD8 HD0 HIO8 HP9 HAD9 HD1 HIO9HAD10 HD2 HIO10 HAD11 HD3 HIO11 12.Host Port Pins HI32 PCIGpio Host Initiator Ready Host Data Bus Direction Bus Command/Byte Enable Host Address BusHost Target Ready Host Data Bus Enable Reserved Host Lock Bus Strobe Parity Error DMA RequestBus Grant Host Address Enable Host Device Select Host Select Acknowledge Hstr Host System Error Host Interrupt RequestBus Request Host Transfer Acknowledge Hreq is deasserted in the same PCI Initialization Device Select Host Read/Data Strobe Hstop HWR/HRWHost Stop Host Write/Read-Write HRD/HDS Address/Data Multiplexed Bus Data Bus Host Bus Clock Active low, open drain output pin Hardware ResetEnhanced Synchronous Serial Interface Host Interrupt a PC2 13.Enhanced Synchronous Serial InterfacePC0 PC1 PC4 SCK0PC3 SRD0 PD2 14.Enhanced Serial Synchronous InterfacePD0 PD1 PD4 SCK1PD3 SRD1 Timers Serial Communications Interface SCI15.Serial Communication Interface Timer 2 Schmitt-Trigger Input/Output- When timer 16.Triple Timer SignalsTimer 0 Schmitt-Trigger Input/Output- When Timer Timer 1 Schmitt-Trigger Input/Output- When Timer Signal Name Type State During Signal Description Reset Jtag and OnCE Interface17.JTAG/OnCE Interface Jtag and OnCE Interface DSP56301 User’s Manual Program Memory Space Memory Configuration Memory Switch Modes-Program Memory Internal Program MemoryInstruction Cache Data Memory Space Program Bootstrap ROMMemory Switch Modes-X Data Memory Memory Configuration Memory Switch Modes-Y Data Memory Internal I/O Space-X Data MemoryInternal Y Data Memory External I/O Space-Y Data Memory Dynamic Memory Configuration Switching DSP56301 RAM Address Ranges by Configuration Sixteen-Bit Compatibility Mode ConfigurationInternal Memory Configuration Summary DSP56301 RAM Configurations Default Memory MapsRAM None 64K $000-$FFF $000-$7FF 16-Bit Space With Default RAM 0, 0 $000-$800 $000-$BFF 16M None 64K $000-$7FF $000-$BFF 16-Bit Space With Switched Program RAM 0, 1 $000-$BFF $000-$7FF Not addressable Instruction Cache Enabled 1, 0 16-Bit Space With Instruction Cache Enabled 1, 0 $000-$3FF $000-$BFF Not addressable Addressable $0400 $0000 Core Configuration Core Configuration Mode Reset Description VectorOperating Modes DSP56301 Operating Modes Mode Description Operating Mode Definitions Address attributes selected default Low. The DSP56301 is written with 24-bit-wide wordsDSP Clkout rate must be 5/3 of the PCI clock Bootstrap Program Status Register SR Central Processor Unit CPU Registers DMA OMR Do Loop Flag Cache EnableSixteen-Bit Arithmetic Mode Do Forever Flag Sixteen-Bit Compatibility Mode Priority Exceptions Exceptions Masked Permitted Scaling ModeScaling Rounding Bit SEquation Mode Interrupt Mask Unnormalized Bit Number Bit Name Reset Value Description LimitScaling Mode Integer Portion Extension Stack Extension Wrap Flag Operating Mode Register OMROperating Mode Register OMR Bit Definitions Stack Extension Enable Stack Extension Overflow Flag Address Trace EnableAddress Attribute Priority Disable Asynchronous Bus Arbitration Enable Synchronize Select Cache Burst Mode EnableMemory Switch Mode Bus Release Timing Chip Operating Mode Configuring InterruptsBit Number Bit Name Reset Value Description Stop Delay Mode External Bus Disable Interrupt Priority Registers Iprc and Iprp Interrupt Table Memory Map Interrupt Priority Level BitsInterrupt Sources VBA$2A VBA$1AVBA$1C VBA$1E Processing Interrupt Source Priorities Within an IPL Interrupt Source Priorities Within an IPLPriority Interrupt Source TIMER1 overflow interrupt Host command interruptTIMER0 overflow interrupt TIMER0 compare interrupt PLL Control Register Pctl Bit Definitions PLL Control Register Pctl Bus Control Register Bus Interface Unit BIU Registers Bus Area 1 Wait State Control Bus Default Area Wait State ControlBus Area 3 Wait State Control Bus Area 2 Wait State Control Bstr Bren BME Bple BPS1 Dram Control Register DCRBRP BRF7 BRF6 BRF3 BRF2 BRF1 10.DRAM Control Register DCR Bit Definitions Bus Column In-Page Wait State Bus Page Logic EnableBus Dram Page Size Bus Row Out-of-page Wait States Address Attribute Registers AAR0-3 Bus Address to CompareBus Number of Address Bits to Compare Bus Program Memory Enable Bus Packing EnableBus Y Data Memory Enable Bus X Data Memory Enable DAM5 DAM4 DAM3 DAM2 DAM1 DAM0 DMA Control Registers 5-0 DCR5-0DIE DTM2 DTM1 DTM0 Dcon 12.DMA Control Register DCR Bit Definitions DMA Interrupt EnableDMA Transfer Mode DTM2-0 Trigger Cleared Transfer Mode After DPR1-0 Channel Priority Number ValueDMA Channel Priority DMA address generation logic, buses, and so forth DMA Continuous Mode Enable OMR CDP1-0 CP1-0 Core PriorityDcon Three-Dimensional Mode DMA Request SourceDRS4-0 Requesting Device Device Identification Register IDR DDS1 DDS0DSS1 DSS0 Number Identity See Note Jtag Identification ID RegisterJtag Boundary Scan Register BSR Version Information Design Center Jtag Boundary Scan Register BSR DSP56301 User’s Manual Programming the Peripherals Peripheral Initialization Steps Data Memory Mapping the Control RegistersData Transfer Methods Polling Interrupts General-Purpose Input/Output Gpio 3 DMAAdvantages and Disadvantages Port B Signals and Registers Port C Signals and Registers Port D Signals and RegistersPort E Signals and Registers Timer Gpio Triple Timer Signals and Registers General-Purpose Input/Output Gpio DSP56301 User’s Manual Host Interface HI32 Features HI32 Features, Core-Side and Host-Side HI32 Features in PCI Mode and Universal Bus Mode Overview Data transfer format converter PCI Configuration SpaceDSP-Side Registers DSP DMA Data Bus DSP Global Data Bus Host-to-DSP Data Path Data Transfer Paths DSP-To-Host Data Path Two least significant bytes of two Hrxm HI32 PCI Master Data Transfer FormatsDpmc FC1 FC0 Transmit Data Transfer Format HctrHTF1 HTF0 Three least significant Hrxs bytes Receive Transfer Data FormatsDSP to Host Data Transfer Format HRF Receive Transfer Data Formats HRST/HRST Reset StatesType Entered when Description DSP-Side Operating Modes PCI Terminate and Reset Dctrhm = $0PCI Mode Dctrhm = $1 HI32 Mode Example 6-1. PCI /DMA Throughput 32-Bit Multfactor Self-Configuration Mode Dctrhm = $5 Gpio Mode Dctrhm = $4 Example 6-3. Self-Configuration Procedure for PCI Mode Host Port Pins PCI Bus Universal Bus ModeHost Port Pin Functionality DSP56301 ISA Slave Master Memory Register Address Mode HI32 DSP-Side Programming ModelHI32 Programming Model, DSP Side Mode Description Value DSP Control Register DctrBit Number Bit Name 10.DSP Control Register Dctr Bit Definitions Host Read/Write Polarity Host Data Strobe ModeHtap Host Transfer Acknowledge Polarity DSP PCI Control Register Dpcr Slave Receive Interrupt EnableSlave Transmit Interrupt Enable Host Command Interrupt Enable IAE Insert Address EnableReceive Buffer Lock Enable 11.DSP PCI Control Register Dpcr Bit Definitions Hserr Master Wait State DisableMaster Access Counter Enable Force Parity Error Interrupt Enable Transfer Complete Interrupt EnableTransaction Termination Interrupt Enable Transaction Abort Interrupt Enable DSP PCI Master Control Register Dpmc BL4BL1 BL0 A PCI Host-to-DSP transaction 12.DSP PCI Master Control Register Dmpc Bit DefinitionsData Transfer Format Control A PCI DSP-to-Host transaction DSP PCI Transaction Address High PCI Data Burst Length AR9 AR8 AR7 AR6 AR5 AR4 AR3 AR2 AR1 AR0 DSP PCI Address Register Dpar13.DSP PCI Address Register Dpar Bit Definitions BE2 BE1 AR1 AR0 PCI Bus CommandC3-0 Command Type DSP PCI Transaction Address Low 2322212019181716 Bit Bit Name Reset Mode Description Number ValueDSP Status Register DSR 14.DSP Status Register DSR Bit Definitions Slave Receive Data Request Srrq UBM Slave Transmit Data Request Mode Description Number ValueHost Command Pending 14. DSP Status Register DSR Bit Definitions Aper Marq Mrrq Mtrq MWS DSP PCI Status Register Dpsr15.DSP PCI Status Register Dpsr Bit Definitions Rdcq MDT Hdtc Trty Tdis TAB MAB PCI Target Retry Master Data TransferredPCI Host Data Transfer Complete PCI Time Out Termination PCI Target Abort PCI Data Parity ErrorPCI Address Parity Error PCI Target Disconnect PCI Master Receive Data Request DSP Receive Data Fifo Drxr15. DSP PCI Status Register Dpsr Bit Definitions PCI Master Wait States DSP Slave Transmit Data Register Dtxs DSP Master Transmit Data Register Dtxm DSP Host Port Gpio Direction Register Dirh DSP Host Port Gpio Data Register Dath16.DATH and Dirh Functionality Host-Side Programming Model 17.HI32 Programming Model, Host-Side RegistersMemory Register Host-Side Programming Model Ignored 18.PCI Bus CommandsExecuted as Command Type HC3/HBE3-HC0/HBE0 20. Host-Side Registers PCI Configuration Address Space 21. Host-Side Registers Universal Bus Mode Address Space19. Host-Side Registers PCI Memory Address Space 13.Host Interface Control Register Hctr 1 HI32 Control Register Hctr Twsd PCI Bit Bit Name Reset Mode Description NumberTarget Wait State Disable 22.Host Interface Control Register Hctr Bit Definitions Host Receive Data Transfer Format Host Transmit Data Transfer Format Inserted Address SFT UBMSlave Fetch Type Data path is lost when the reset state is Universal Bus mode Fetch SFT =Cleared when the DSP56300 core writes to Reset, and Strq and Hstrhrrq are cleared Dmae UBM Dmae HaenHirq Hirq Pin Hdrq pin Receive Req uest EnableRreq UBM Dmae Treq Rreq UBM UBM UBM UBM UBM UBM PCI PCI PCI PCI PCI PCI Host Interface Status Register HstrHreq Hint HF5 HF4 HF3 Trdy Treq Rreq Hreq 23.Host Interface Status Register Hstr Bit DefinitionsHost Request Host interrupt a Host Receive Data Request Host Transmit Data RequestTransmitter Ready 15.Host Command Vector Register Hcvr Host Command Vector Register Hcvr Hnmi UBM 24.Host Command Vector Register Hcvr Bit DefinitionsHost Command Vector Bit Bit Name Reset Value Mode Description Number Host Slave Receive Data Register Hrxs Host CommandWhen the DSP56300 core acknowledges the host command Host Master Receive Data Register Hrxm Host Transmit Data Register Htxr Universal Bus mode Dctrhm = $2 or $3 PCI Mode Dctrhm = $1 DPR Fbbc Device ID/Vendor ID Configuration Register CDID/CVIDStatus/Command Configuration Register CSTR/CCMR DPE SSE RMA RTA STA Received Master Abort Detected Parity ErrorSignaled System Error Signalled Target Abort Bus Master Enable System Error EnableWait Cycle Control hardwired to zero Parity Error Response Class Code/Revision ID Configuration Register CCCR/CRID Read-only bits that identify the layout of bytes $10-$3F Header Type hardwired to $00HT7 HT6 HT5 HT4 HT3 HT2 HT1 HT0 HT7-0 Latency Timer High Cache Line SizeCcls Memory Base Address High/Low Memory Space Base Address Configuration Register CbmaUniversal Bus Mode Base Address PM8 PM7 PM6 PM5 PM4 MS1 MS0 MSI Memory Space Hardwired to zeros 29. Memory Space Base Address Configuration Register CbmaMemory Base Address Low Hardwired to zeros Pre-Fetch Hardwired to zero Example 6-5. Code for Setting the Csid Maxlat Interrupt Line-Interrupt Pin Configuration RegisterCILPIL5 IL4 IL1 IL0 UBM Hrsp HI32 Programming Model/Quick ReferenceHS PH PS Dctr Hcie Dpcr Mtie ClrtRble Hact DpmcDpar DSR HCP Rdcq Dpsr AperDper Hdtc SFT TreqDmae ISA/EISA Hrxs HcvrHnmi Hrxm Cbma MSI Ccmr RMACccr Chty SC0 GDB DDB RclkRsma Rsmb Tsma Tclk STD Tsmb TX0 CRA Essi Enhancements Serial Clock SCK Essi Data and Control SignalsSerial Transmit Data Signal STD Serial Receive Data Signal SRD Serial Control Signal SC1 Serial Control Signal SC0 Mode and Signal Definitions Control Bits Essi SignalsSYN TE0 TE1 TE2 SC0 SC1 SC2 SCK STD SRD Initialization Serial Control Signal SC2Essi After Reset Operation Exceptions Operation Write data to all enabled transmit registers Operating Modes Normal, Network, and On-Demand Normal/Network/On-Demand Mode Selection Frame Sync Signal Format Synchronous/Asynchronous Operating ModesFrame Sync Selection Frame Sync Length for Multiple Devices Word Length Frame Sync and Data Word TimingFrame Sync Polarity Flags Byte Format LSB/MSB for the Transmitter PM7 PM6 PM5 PM4 PM3 PM2 PM1 PM0 Essi Programming ModelEssi Control Register a CRA WL2 WL1 WL0 ALC Essi Word Length Selection Essi Control Register a CRA Bit DefinitionsSelect SC1 Word Length Control Prescale Modulus Select Alignment ControlFrame Rate Divider Control Prescaler Range Tclock CRBTE1 CRBOF0 SSISRIF0Crbsyn = Rclock ESSI0 X$FFFFB6, ESSI1 X$FFFFA6 Essi Control Register B CRBShfd OF1 OF0 Essi Control Register B CRB Bit Definitions TIE Transmit Interrupt EnableReceive Enable Transmit 0 Enable Synchronous/Asynchronous Transmit 1 EnableTransmit 2 Enable Mode Select FSL1 FSL0 OF0 Serial Control DirectionOF1 Serial Output Flag Serial Clock RX, TX Frame Sync RX, TX Serial Data Serial Clock RX Frame Sync RX Serial DataTX Frame Sync TX Serial Data Essi Bit CRB SYN Bit Operation Bit Operation SSI Control Register B CRB READ/WRITEReceiver Interrupt or DMA Request and Flags Set Frame Sync FSL0 = 0, FSL1 = Data Flags Frame Sync FSL0 = 0, FSL1 = Data Out Flags Receive Data Register Full Receiver Overrun Error FlagTransmitter Underrun Error Flag Essi Status Register Ssisr Serial Input Flag Essi Receive Shift RegisterReceive Frame Sync Flag Transmit Frame Sync Flag Essi Transmit Shift Registers Essi Receive Data Register RX Transmit Registers Receive Registers MSB Transmit Middle Byte Transmit Low Byte Register 24 BitWL0 Least Significant TS9 TS8 TS7 TS6 TS5 TS4 TS3 TS2 TS1 TS0 Essi Transmit Data Registers TX2-0Essi Time Slot Register TSR Transmit Slot Mask Registers TSMA, Tsmb 15.ESSI Transmit Slot Mask Register B Tsmb RS15 RS14 RS13 RS12 RS11 RS10 Receive Slot Mask Registers RSMA, RsmbRS7 RS6 RS1 RS0 Port Control Registers Pcrc and Pcrd Gpio Signals and Registers Essi Port Signal Configurations Port Direction Registers Prrc and PrrdESSI0/ESSI1 20.Port Data Registers Pdrc X$FFFFBD Pdrd X $FFFFAD Port Data Registers Pdrc and Pdrd Serial Communication Interface SCI Serial Communication Interface SCI Synchronous Mode Asynchronous ModeMultidrop Mode Transmitting Data and Address Characters I/O SignalsWired-OR Mode Address Mode Wakeup Receive Data RXD Transmit Data TXDSCI Serial Clock Sclk Woms RWU Wake SBK Ssftd SCI After ResetSCI Registers After Reset Reie Sckp Stir Tmie TIE RIE Ilie SCI Initialization Preamble, Break, and Data Transmission Priority Exceptions Bootstrap Loading Through the SCI Boot Mode 2 or a SCI Programming Model Bit Asynchronous 1 Start, 8 Data, 1 Even Parity, 1 Stop Bit Synchronous Data Shift Register ModeWDS2 WDS1 WDS0 Bit Asynchronous 1 Start, 8 Data, 1 Stop SCI Data Word Formats Ssftd = 0 SCI Control Register SCR ReieStir Tmie TIE RIE Ilie Woms RWU Wake SBK Ssftd WDS2 Idle Line Interrupt Enable Timer Interrupt EnableSCI Transmit Interrupt Enable SCI Receive Interrupt Enable Receiver Enable Wired-OR Mode SelectWoms SCI Shift Direction Receiver Wakeup EnableWakeup Mode Select Send Break Mode Word Formats Word SelectWDS1 WDS0 SCI Status Register SSR SCI Status Register SCI Status Register SSR Bit DefinitionsIdle Rdrf Tdre Trne Idle Line Flag TdreTransmitter Empty Sclk SCI Clock Control Register SccrTCM RCM SCP COD TCM RCM Sckp = 0 + Sckp = Bit CounterDivide by CD11-0 X1 Clock X16 Clock Sckp = RX, TX Data Ssftd = SCI Data Registers SCI Receive Register SRXSCI Receive Data Shift Register SCI Transmit Register STX Port E Control Register Pcre PE2 PE1 PE0Sclk TXD RXD PDRE1 PDRE0 Port E Direction Register PrrePort E Data Register Pdre PRRE1 PRRE0 Gpio Signals and Registers DSP56301 User’s Manual Triple Timer Module Triple Timer Module Tpcr Triple Timer Module Block DiagramIndividual Timer Block Diagram GDB Timer Module Block Diagram Timer After Reset Timer Exceptions Timer Initialization TCSR0 Tcie TIO Triple Timer ModesTimer Gpio Mode TC3 TC2 TC1 TC0 Mode 0 internal clock, no timer output TRM = TLRTCR Tcpr Timer Pulse Mode Mode 1 internal clock TRM =Output Pulse width = timer clock Period = write preload = write compare Clock CLK/2 or prescale CLK Timer Toggle ModeMode 2 internal clock TRM = 1 first event Toggle Timer Mode 2 internal clock TRM = = write preload= write compare Clock CLK/2 or prescale CLK TIO Cpuclk + Timer Event Counter ModeMode 3 internal clock TRM = Input External = write compare Clock 10.Event Counter Mode, TRM = Input width Measurement Signal Measurement ModesMeasurement Input Width Mode Input Mode 4 internal clock TRM = 1 first event Mode 4 internal clock TRM = Input period Measurement Internal Measurement Input Period ModeMode 5 internal clock TRM = First event = write preload = write compare Counting, does May occur TOF=1Reads TCR period Internal Measurement Capture ModeMode 6 internal clock TRM = Interrupt Service reads TCR delay = M N clock periods Pulse Width Modulation PWM, Mode PWMPulse width modulation 16.Pulse Width Modulation Toggle Mode, TRM = Mode 7 internal clock TRM = 17.Pulse Width Modulation Toggle Mode, TRM = Output Internal Watchdog Pulse ModeWatchdog Modes Pulse Watchdog Mode 9 internal clock TRM = Software does not reset watchdog timer watchdog times out= write preload First event Toggle Watchdog Toggle ModeMode 10 internal clock TRM = Watchdog Output Prescaler Counter Triple Timer Module Programming ModelSpecial Cases DMA Trigger Tplr = $FFFF83 Timer Prescaler LoadRegister Tplr 23 22 21 20 19 18 17 Prescaler Preload Value Timer Prescaler Load Register TplrPrescaler Source PS1 PS0 TRM INV Timer Prescaler Count Register TpcrTimer Control/Status Register Tcsr TCF TOF PCE Data Output Timer Compare FlagTimer Overflow Flag Prescaler Clock Enable Timer Reload Mode DirectionInverter Number Function Timer Control TIO Programmed as Input TIO Programmed as Output Mode INV = Timer Compare Interrupt EnableTimer Overflow Interrupt Enable Timer Enable Timer Load Register TLR Pulse generated by Timer has Timer has negativePositive polarity Timer Count Register TCR Timer Compare Register Tcpr Appendix a DSP56301 User’s Manual HBS Can be stopped Hdben Aarv Mscte EQU LOOP0 Lbld Lble LOOP8 LOOP11 Rep Mac x0,x1,a x,lr0+ ORG PL,PL Patterns Write to Destination DSP56301 User’s Manual Programming Reference Chapter B Table B-1.Guide to Programming Sheets Internal I/O Memory Map Table B-2. Internal I/O Memory Map X Data MemoryBit Address Register Name Peripheral Bit Address Register Name Table B-2.Internal I/O Memory Map X Data Memory $FFCA $FFFFCA $FFCD $FFFFCD$FFCC $FFFFCC $FFCB $FFFFCB $FFB9 $FFFFB9 Essi $FFBC $FFFFBC$FFBB $FFFFBB $FFBA $FFFFBA $FFA9 $FFFFA9 Essi $FFAC $FFFFAC$FFAB $FFFFAB $FFAA $FFFFAA $FF8F $FFFF8F $FFFF92$FFFF91 $FFFF90 Table B-3. Interrupt Sources Interrupt Sources and Priorities VBA$6E Table B-3.Interrupt SourcesVBA$6A VBA$6C Table B-4.Interrupt Source Priorities Within an IPL Nonmaskable Host Command Interrupt ESSI0 receive last slot interrupt Figure B-1.Status Register SR Programming Sheets Burst Mode Enable External Bus DisableStop Delay Memory Switch Mode Irqa Mode Irqd ModeIrqc Mode Irqb Mode Triple Timer IPL Host IPLInterrupt Priority Register Iprp $FFFFFE Read/Write Crystal Range Bit Xtlr PLL Control Register Pctl $FFFFFD Read/Write Bus Lock Hold, Bit Default Area Wait Control, BitsBus Control Register BCR $FFFFFB Read/Write Bus Request Hold, Bit Dram Control Register DCR $FFFFFA Read/Write Bus Program Memory Enable, Bit Bus Packing Enable, BitBus Y Data Memory Enable, Bit Bus X Data Memory Enable, Bit DMA Control Registers DCR5-DCR0 Reset = $000000 $FFFFE4, X$FFFFE8, X$FFFFEC Read/Write Application DSP Control Register Dctr Read/Write Address X FFFFC5 DSP PCI Control Register Dpcr Address XFFFFC6 Read/Write = Enables master receive interrupts Figure B-12.DSP PCI Master Control Register Dpmc Figure B-13.DSP PCI Address Register Dpar PCI Bus Command, Bits HI32 Control Register Hctr Read/Write Host Non-Maskable Interrupt, Bit HI32 Command Vector Register Hcvr Read/Write System Error Enable, Bit Detected Parity Error, BitSignaled System Error, Bit Signalled Target Abort, Bit Cache Line Size, Bits Latency Timer High, BitsRead/Write Header Type, Bits Memory Space Indicator, Bit HI32 Memory Space Base Address Configuration Register CbmaReset = $00000000 PCI Mode Base Address High, Bits Pre-fetch, Bit Subsystem ID Register, Bits 31-16 Specifies the subsystem ID ESSI1-X$FFFFA5 Read/Write Essi Control Register a CRAx ESSI0-X$FFFFB5 Read/Write Essi Control Register B CRBx ESSI0-X$FFFFB6 Read/WriteESSI1-X$FFFFA6 Read/Write ESSI1-X$FFFFA3 Read/Write Essi Transmit Slot Mask a TSMA0-1 ESSI0-X$FFFFB4 Read/WriteESSI1-X$FFFFA4 Read/Write Essi Transmit Slot Mask B TSMB0-1 ESSI0-X$FFFFB3 Read/Write SCI Control Register SCR $FFFF9C Read/Write SCI Clock Control Register Sccr Address X$FFFF9B Read/Write Receiver Clock Mode/SourceClock Out Divider Timer Prescaler Load Register Tplr $FFFF83 Read/Write Figure B-25.Timer Prescaler Load Register Tplr TCSR1$FFFF8B Read/Write TCSR2$FFFF87 Read/Write Timer Control/Status Register TCSR0$FFFF8F Read/Write TLR1-X$FFFF8A Write Only TLR2-X$FFFF86 Write Only Timer Load Register TLR0-2 TLR0-X$FFFF8E Write Only Port B HI08 Host Data Direction Register Hddr X$FFFFC8 WriteHost Data Register HDR $FFFFC9 Write Port C Gpio Data Register Pdrc $FFFFBD Read/Write Port C ESSI0Port C Control Register Pcrc $FFFFBF Read/Write Port C Direction Register Prrc $FFFFBE Read/Write Port D Gpio Data Register Pdrd $FFFFAD Read/Write Port D ESSI1Port D Control Register Pcrd $FFFFAF Read/Write Port D Direction Register Prrd $FFFFAE Read/Write Port E Gpio Data Register Pdre $FFFF9D Read/Write Port E SCIPort E Control Register Pcre $FFFF9F Read/Write Port E Direction Register Prre $FFFF9E Read/Write Programming Sheets DSP56301 User’s Manual Index Index-2 DSP56301 User’s Manual Index-3 Index-4 DSP56301 User’s Manual Index-5 Index-6 DSP56301 User’s Manual Index-7 Index-8 DSP56301 User’s Manual Index-9 Index-10 DSP56301 User’s Manual Index-11 Index-12 DSP56301 User’s Manual Index-13 Index-14 DSP56301 User’s Manual Index-15 Index-16 DSP56301 User’s Manual