Motorola DSP56301 user manual DSP Control Register Dctr Bit Definitions

HI32 DSP-Side Programming Model

Table 6-10.DSP Control Register (DCTR) Bit Definitions (Continued)

Bit Number	Bit Name	Reset	Mode			Description
		Value
19	HIRD	0	UB	Host Interrupt Request Drive Control
				Controls the output drive of the HIRQ pin when the HI32 is in a
				Universal Bus mode (DCTR[HM] = $2 or $3). When HIRD is cleared,
				the HIRQ pin is an open-drain output—that is, driven low when
				asserted, released (high impedance) when deasserted. When HIRD is
				set, the HIRQ pin is always driven. The value of HIRD can be changed
				only when DSR[HACT] = 0. HIRD is ignored when the HI32 is not in a
				Universal Bus mode (DCTR[HM] ≠ $2 or $3).
				Note: The HDSM, HRWP, HTAP, HDRP, HRSP, HIRH, and HIRD
				bits affect the host port pins directly. To assure proper
				operation, these pins can be changed only when DSR[HACT]
				= 0. The HM[2–0] bits must not be changed together with
				these bits (that is, in the same core write).
18	HIRH	0	UB	Host Interrupt Request Handshake Mode
				Controls the handshake mode of the HIRQ pin when the HI32 is in a
				Universal Bus mode (DCTR[HM] = $2 or $3). The HI32 asserts HIRQ
				when a host interrupt request (receive and/or transmit) is generated in
				the HI32. When HIRH is cleared and a host interrupt request is
				generated, HIRQ is asserted for the number of DSP56300 core clock
				cycles specified CLAT[LT[7–0]] and then deasserted. The duration of
				the HIRQ pulse is expressed as follows:
				HIRQ_PULSE_WIDTH = (LT[7–0]_Value + 1) • DSP56300_Core_clock_cycle
				If HIRH is set,	HIRQ	is deasserted when the interrupt request source is
				cleared (by the corresponding host data access), masked (by TREQ = 0
				or RREQ = 0), or disabled by the DMA enable bit HCTR[DMAE]. The
				value of HIRH can be changed only when DSR[HACT] = 0. HIRH is
				ignored when the HI32 is not in a Universal Bus mode (DCTR[HM] ≠
				$2 or $3).
17	HRSP	0	UB	Host Reset Polarity
				Controls the polarity of the HRST pin when the HI32 is in a Universal
				Bus or the GPIO mode (DCTR[HM] = $2, $3, or $4). If HRSP is cleared,
				the HRST pin is active high and the HI32 is reset if the HRST pin is high
				(that is, asserted). If HRSP is set, the HRST pin is active low and the
				HI32 is reset if the HRST pin is low (that is, asserted). The value of
				HRSP can change only when DSR[HACT] = 0. HRSP is ignored in PCI
				mode (DCTR[HM] = $1).
16	HDRP	0	UB	Host DMA Request Polarity
				Controls the polarity of HDRQ pin when the HI32 is in a Universal Bus
				mode (DCTR[HM] = $2 or $3). If HDRP is cleared, the HDRQ pin is
				active high and the HI32 requests DMA service by driving the HDRQ
				pin high (that is, asserted). If HDRP is set, the HDRQ pin is active low
				and the HI32 requests DMA service by driving the HDRQ pin low (that
				is, asserted). The value of HDRP can change only when DSR[HACT] =
				0. HDRP is ignored when the HI32 is not in a Universal Bus mode
				(DCTR[HM] ≠ $2 or $3).

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