DSP Control Register Dctr Bit Definitions

HI32 DSP-Side Programming Model

Table 6-10.DSP Control Register (DCTR) Bit Definitions (Continued)

Bit Number	Bit Name	Reset	Mode			Description
Bit Number	Bit Name	Value	Mode			Description
		Value


19	HIRD	0	UB	Host Interrupt Request Drive Control
				Controls the output drive of the HIRQ pin when the HI32 is in a
				Universal Bus mode (DCTR[HM] = $2 or $3). When HIRD is cleared,
				the HIRQ pin is an open-drain output—that is, driven low when
				asserted, released (high impedance) when deasserted. When HIRD is
				set, the HIRQ pin is always driven. The value of HIRD can be changed
				only when DSR[HACT] = 0. HIRD is ignored when the HI32 is not in a
				Universal Bus mode (DCTR[HM] ≠ $2 or $3).
				Note: The HDSM, HRWP, HTAP, HDRP, HRSP, HIRH, and HIRD
				bits affect the host port pins directly. To assure proper
				operation, these pins can be changed only when DSR[HACT]
				= 0. The HM[2–0] bits must not be changed together with
				these bits (that is, in the same core write).

18	HIRH	0	UB	Host Interrupt Request Handshake Mode
				Controls the handshake mode of the HIRQ pin when the HI32 is in a
				Universal Bus mode (DCTR[HM] = $2 or $3). The HI32 asserts HIRQ
				when a host interrupt request (receive and/or transmit) is generated in
				the HI32. When HIRH is cleared and a host interrupt request is
				generated, HIRQ is asserted for the number of DSP56300 core clock
				cycles specified CLAT[LT[7–0]] and then deasserted. The duration of
				the HIRQ pulse is expressed as follows:
				HIRQ_PULSE_WIDTH = (LT[7–0]_Value + 1) • DSP56300_Core_clock_cycle

				If HIRH is set,	HIRQ	is deasserted when the interrupt request source is
				cleared (by the corresponding host data access), masked (by TREQ = 0
				or RREQ = 0), or disabled by the DMA enable bit HCTR[DMAE]. The
				value of HIRH can be changed only when DSR[HACT] = 0. HIRH is
				ignored when the HI32 is not in a Universal Bus mode (DCTR[HM] ≠
				$2 or $3).

17	HRSP	0	UB	Host Reset Polarity
				Controls the polarity of the HRST pin when the HI32 is in a Universal
				Bus or the GPIO mode (DCTR[HM] = $2, $3, or $4). If HRSP is cleared,
				the HRST pin is active high and the HI32 is reset if the HRST pin is high
				(that is, asserted). If HRSP is set, the HRST pin is active low and the
				HI32 is reset if the HRST pin is low (that is, asserted). The value of
				HRSP can change only when DSR[HACT] = 0. HRSP is ignored in PCI
				mode (DCTR[HM] = $1).

16	HDRP	0	UB	Host DMA Request Polarity
				Controls the polarity of HDRQ pin when the HI32 is in a Universal Bus
				mode (DCTR[HM] = $2 or $3). If HDRP is cleared, the HDRQ pin is
				active high and the HI32 requests DMA service by driving the HDRQ
				pin high (that is, asserted). If HDRP is set, the HDRQ pin is active low
				and the HI32 requests DMA service by driving the HDRQ pin low (that
				is, asserted). The value of HDRP can change only when DSR[HACT] =
				0. HDRP is ignored when the HI32 is not in a Universal Bus mode
				(DCTR[HM] ≠ $2 or $3).

6-24	DSP56301 User’s Manual

DSP56301 specifications

The Motorola DSP56301 is a highly efficient digital signal processor, specifically engineered for real-time audio and speech processing applications. This DSP is part of Motorola's renowned DSP56300 family, which is recognized for its innovative features and outstanding performance in the realm of digital signal processing.

One of the main features of the DSP56301 is its ability to handle complex computations at high speeds. With a maximum clock frequency of 66 MHz, it delivers fast performance, enabling it to process audio signals in real time. The chip is built on a 24-bit architecture, which allows for high-resolution audio processing. This is particularly beneficial in applications such as telecommunications, consumer audio devices, and professional audio equipment, where precision is paramount.

The DSP56301 boasts a comprehensive instruction set that includes efficient mathematical operations, which are essential for digital filters and audio effects processing. One of the key innovations of this device is its dual data path architecture, which permits simultaneous processing of multiple data streams. This feature significantly enhances the device's throughput and responsiveness, making it suitable for demanding applications such as voice recognition and synthesis.

In terms of memory regions, the DSP56301 includes several on-chip memory categories, such as program memory, data memory, and a specialized memory for coefficients. The architecture's support for external memory expansion further increases its versatility, allowing designers to tailor systems to their specific requirements.

The DSP56301 implements advanced features such as a powerful on-chip hardware multiplier and accumulator, simplifying complex mathematical tasks and accelerating the execution of algorithms. Its flexible interrupt system enhances its capability to respond to time-sensitive operations, while the integrated serial ports facilitate efficient data communication with external devices.

Power consumption is also a vital characteristic of the DSP56301. It is designed with energy efficiency in mind, allowing for extended operation in battery-powered devices. The chip’s low power requirements are particularly advantageous in portable audio devices and other applications where energy conservation is crucial.

In conclusion, the Motorola DSP56301 is an exceptional digital signal processor that combines high processing power, flexibility, and efficiency. Its main features, advanced technologies, and robust architecture make it a top choice for developers seeking to create sophisticated audio and signal processing systems. With its enduring legacy in the industry, the DSP56301 continues to be relevant in a variety of modern applications, ensuring it remains a valuable tool for engineers and designers.

Motorola DSP56301 user manual DSP Control Register Dctr Bit Definitions

Models: DSP56301

Table 6-10.DSP Control Register (DCTR) Bit Definitions (Continued)

Mode

Host Interrupt Request Drive Control

Host Interrupt Request Handshake Mode

HIRQ

Host Reset Polarity

Host DMA Request Polarity

DSP56301 specifications