HI32 DSP-Side Programming Model

 

 

 

 

Table 6-15.DSP PCI Status Register (DPSR) Bit Definitions (Continued)

 

 

 

 

Bit Number

Bit Name

Reset Value

Description

 

 

 

 

 

 

 

 

3

 

0

Reserved. Write to 0 for future compatibility.

2

MRRQ

0

PCI Master Receive Data Request

 

 

 

Indicates that the DSP receive data FIFO (DRXR) contains data read from

 

 

 

the host bus by the HI32 master. When the HI32, as master, reads data

 

 

 

from the host bus to the host-to-DSP FIFO (HTXR-DRXR), MRRQ is set.

 

 

 

MRRQ is cleared if the DRXR is emptied by DSP56300 core reads or the

 

 

 

data to be read from the DRXR is slave data. When MRRQ is set and

 

 

 

DPCR[MRIE] is set, a master receive data interrupt request is generated.

 

 

 

When MRRQ is set and when enabled by an DSP56300 core DMA

 

 

 

channel, a master receive data DMA request is generated. Hardware,

 

 

 

software and personal software resets clear MRRQ.

 

 

 

 

1

MTRQ

1

PCI Master Transmit Data Request

 

 

 

Indicates that the DSP master transmit data FIFO (DTXM) is not full and

 

 

 

can be written by the DSP56300 core. MTRQ is cleared when the DTXM

 

 

 

is filled by core writes. MTRQ is set when data is output from the

 

 

 

DTXM-HRXM FIFO to the host bus. When MTRQ is set and DPCR[MTIE]

 

 

 

is set, a master transmit data interrupt request is generated. When

 

 

 

enabled by a DSP56300 core DMA channel, a master transmit data DMA

 

 

 

request is generated. Hardware, software, and personal software resets

 

 

 

set MTRQ. In the personal software reset state MTRQ = 0.

 

 

 

 

0

MWS

0

PCI Master Wait States

 

 

 

Indicates that the HI32, as master in a PCI transaction, inserts wait states

 

 

 

to extend the current data phase (or the first data phase if the transaction

 

 

 

is not yet initiated) by deasserting HIRDY because it cannot guarantee

 

 

 

completion of the next data phase. MWS is enabled when the

 

 

 

DPCR[MWSD] bit is cleared. MWS is set in a PCI write transaction when

 

 

 

there is only one word in the HI32-to-host data path. MWS is set in a PCI

 

 

 

read transaction, if there is only one empty location in the host-to-DSP

 

 

 

data path. This has many applications. For example, the Master Transfer

 

 

 

Terminate (MTT) bit in the DSP PCI Control Register (DPCR) generates a

 

 

 

transaction termination initiated by the PCI master. The DSP56300 core

 

 

 

can set MTT when MWS is set to terminate a transaction after the transfer

 

 

 

of a specific number of words. After MTT is set the HI32 completes the

 

 

 

data phase and terminates the transaction. Hardware, software, and

 

 

 

personal software resets clear MWS.

 

 

 

 

6.7.7DSP Receive Data FIFO (DRXR)

The 24-bit wide DSP Receive Data Register (DRXR) is the output stage of the host-to-DSP data path FIFO for host-to-DSP data transfers (refer to Section 6.3, Data Transfer Paths, on page 6-6). The DRXR contains master data, that is, data read by the HI32 as PCI master from an external target to be read if DPSR[MRRQ] is set. MRRQ is cleared if the data in the DRXR is slave data or when the host-to-DSP data path FIFO is emptied by DSP56300 core reads. The DSP56300 core can set the DPCR[MRIE] bit to cause a host receive data interrupt when MRRQ is set.

The DRXR contains slave data—that is, data written to the HI32 from the host bus—to be

read if DSR[SRRQ] is set. DSR[SRRQ] is cleared if the data in the DRXR is master data or

Host Interface (HI32)

6-41

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Motorola DSP56301 DSP Receive Data Fifo Drxr, DSP PCI Status Register Dpsr Bit Definitions, PCI Master Wait States
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DSP56301 specifications

The Motorola DSP56301 is a highly efficient digital signal processor, specifically engineered for real-time audio and speech processing applications. This DSP is part of Motorola's renowned DSP56300 family, which is recognized for its innovative features and outstanding performance in the realm of digital signal processing.

One of the main features of the DSP56301 is its ability to handle complex computations at high speeds. With a maximum clock frequency of 66 MHz, it delivers fast performance, enabling it to process audio signals in real time. The chip is built on a 24-bit architecture, which allows for high-resolution audio processing. This is particularly beneficial in applications such as telecommunications, consumer audio devices, and professional audio equipment, where precision is paramount.

The DSP56301 boasts a comprehensive instruction set that includes efficient mathematical operations, which are essential for digital filters and audio effects processing. One of the key innovations of this device is its dual data path architecture, which permits simultaneous processing of multiple data streams. This feature significantly enhances the device's throughput and responsiveness, making it suitable for demanding applications such as voice recognition and synthesis.

In terms of memory regions, the DSP56301 includes several on-chip memory categories, such as program memory, data memory, and a specialized memory for coefficients. The architecture's support for external memory expansion further increases its versatility, allowing designers to tailor systems to their specific requirements.

The DSP56301 implements advanced features such as a powerful on-chip hardware multiplier and accumulator, simplifying complex mathematical tasks and accelerating the execution of algorithms. Its flexible interrupt system enhances its capability to respond to time-sensitive operations, while the integrated serial ports facilitate efficient data communication with external devices.

Power consumption is also a vital characteristic of the DSP56301. It is designed with energy efficiency in mind, allowing for extended operation in battery-powered devices. The chip’s low power requirements are particularly advantageous in portable audio devices and other applications where energy conservation is crucial.

In conclusion, the Motorola DSP56301 is an exceptional digital signal processor that combines high processing power, flexibility, and efficiency. Its main features, advanced technologies, and robust architecture make it a top choice for developers seeking to create sophisticated audio and signal processing systems. With its enduring legacy in the industry, the DSP56301 continues to be relevant in a variety of modern applications, ensuring it remains a valuable tool for engineers and designers.
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