Central Processor Unit (CPU) Registers

Table 4-3.Status Register Bit Definitions (Continued)

Bit Number

Bit Name

Reset Value

 

Description

 

 

 

 

 

 

 

 

14

DM

0

Double-Precision Multiply Mode

 

 

 

Enables four multiply/MAC operations to implement a double-precision

 

 

 

algorithm that multiplies two 48-bit operands with a 96-bit result. Clearing

 

 

 

the DM bit disables the mode.

 

 

 

Note:

The Double-Precision Multiply mode is supported to maintain

 

 

 

 

object code compatibility with devices in the DSP56000 family. For

 

 

 

 

a more efficient way of executing double precision multiply, refer

 

 

 

 

to the chapter on the Data Arithmetic Logic Unit in the DSP56300

 

 

 

 

Family Manual.

 

 

 

In Double-Precision Multiply mode, the behavior of the four specific

 

 

 

operations listed in the double-precision algorithm is modified. Therefore,

 

 

 

do not use these operations (with those specific register combinations) in

 

 

 

Double-Precision Multiply mode for any purpose other than the double

 

 

 

precision multiply algorithm. All other Data ALU operations (or the four

 

 

 

listed operations, but with other register combinations) can be used.

 

 

 

The double-precision multiply algorithm uses the Y0 Register at all stages.

 

 

 

Therefore, do not change Y0 when running the double-precision multiply

 

 

 

algorithm. If the Data ALU must be used in an interrupt service routine, Y0

 

 

 

should be saved with other Data ALU registers to be used and restored

 

 

 

before the interrupt routine terminates.

 

 

 

 

13

SC

0

Sixteen-Bit Compatibility Mode

 

 

 

Affects addressing functionality, enabling full compatibility with object code

 

 

 

written for the DSP56000 family. When SC is set, MOVE operations to/from

 

 

 

any of the following PCU registers clear the eight MSBs of the destination:

 

 

 

LA, LC, SP, SSL, SSH, EP, SZ, VBA and SC. If the source is either the SR

 

 

 

or OMR, then the eight MSBs of the destination are also cleared. If the

 

 

 

destination is either the SR or OMR, then the eight MSBs of the destination

 

 

 

are left unchanged. To change the value of one of the eight MSBs of the SR

 

 

 

or OMR, clear SC.

 

 

 

SC also affects the contents of the Loop Counter Register. If SC is cleared

 

 

 

(normal operation), then a loop count value of zero causes the loop body to

 

 

 

be skipped, and a loop count value of $FFFFFF causes the loop to execute

 

 

 

the maximum number of 224 – 1 times. If the SC bit is set, a loop count

 

 

 

value of zero causes the loop to execute 216 times, and a loop count value

 

 

 

of $FFFFFF causes the loop to execute 216 – 1 times.

 

 

 

Note:

Due to pipelining, a change in the SC bit takes effect only after

 

 

 

 

three instruction cycles. Insert three NOP instructions after the

 

 

 

 

instruction that changes the value of this bit to ensure proper

 

 

 

 

operation.

 

 

 

 

12

 

0

Reserved. Write to 0 for future compatibility.

 

 

 

 

 

Core Configuration

4-9

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Image 83
Motorola DSP56301 user manual Sixteen-Bit Compatibility Mode
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DSP56301 specifications

The Motorola DSP56301 is a highly efficient digital signal processor, specifically engineered for real-time audio and speech processing applications. This DSP is part of Motorola's renowned DSP56300 family, which is recognized for its innovative features and outstanding performance in the realm of digital signal processing.

One of the main features of the DSP56301 is its ability to handle complex computations at high speeds. With a maximum clock frequency of 66 MHz, it delivers fast performance, enabling it to process audio signals in real time. The chip is built on a 24-bit architecture, which allows for high-resolution audio processing. This is particularly beneficial in applications such as telecommunications, consumer audio devices, and professional audio equipment, where precision is paramount.

The DSP56301 boasts a comprehensive instruction set that includes efficient mathematical operations, which are essential for digital filters and audio effects processing. One of the key innovations of this device is its dual data path architecture, which permits simultaneous processing of multiple data streams. This feature significantly enhances the device's throughput and responsiveness, making it suitable for demanding applications such as voice recognition and synthesis.

In terms of memory regions, the DSP56301 includes several on-chip memory categories, such as program memory, data memory, and a specialized memory for coefficients. The architecture's support for external memory expansion further increases its versatility, allowing designers to tailor systems to their specific requirements.

The DSP56301 implements advanced features such as a powerful on-chip hardware multiplier and accumulator, simplifying complex mathematical tasks and accelerating the execution of algorithms. Its flexible interrupt system enhances its capability to respond to time-sensitive operations, while the integrated serial ports facilitate efficient data communication with external devices.

Power consumption is also a vital characteristic of the DSP56301. It is designed with energy efficiency in mind, allowing for extended operation in battery-powered devices. The chip’s low power requirements are particularly advantageous in portable audio devices and other applications where energy conservation is crucial.

In conclusion, the Motorola DSP56301 is an exceptional digital signal processor that combines high processing power, flexibility, and efficiency. Its main features, advanced technologies, and robust architecture make it a top choice for developers seeking to create sophisticated audio and signal processing systems. With its enduring legacy in the industry, the DSP56301 continues to be relevant in a variety of modern applications, ensuring it remains a valuable tool for engineers and designers.
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