Motorola DSP56301 user manual Figure B-12.DSP PCI Master Control Register Dpmc

Programming Sheets

Application:	Date:
	Programmer:

Sheet 3 of 10

Host Processor (HI32)

Data Transfer Format Control, Bits 23–22HI32-PCI data transfer formats, as follows:

PCI DSP-to-Host (data in DTXM)

00 32-bit data mode

01Data to HAD[31–0] right-aligned and zero extended in MSB

10Data to HAD[31–0] right-aligned and sign extended in MSB

11Data to HAD[31–0] left-aligned and zero filled in LSB

PCI Host-to-DSP

00 32-bit data mode

013 LSB PCI data to DRXR from HAD[23–0]

103 LSB PCI data to DRXR from HAD[23–0]

113 MSB PCI data to DRXR from HAD[31–8]

Note: LSB = least significant byte; MSB = most significant byte

PCI Data Burst Length, Bits 21–16

The value is the desired number of burst accesses – 1.

DSP PCI Transaction Address (High), Bits 15–0

The two most significant bytes of the 32-bit

PCI transaction address.

23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
FC1	FC0	BL5	BL4	BL3	BL2	BL1	BL0	AR31	AR30	AR29	AR28	AR27	AR26	AR25	AR24	AR23	AR22	AR21	AR20	AR19	AR18	AR17	AR16

DSP PCI Master Control Register (DPMC) Address: X:FFFFC7 Read/Write

Reset = $000000

Note: All bits work only in PCI mode (DCTR[HM] = $1). You can write to the DPMC only if MARQ is set or the system is in Self-Configuration mode.

Figure B-12.DSP PCI Master Control Register (DPMC)

B-24 DSP56301 User’s Manual