External Memory Expansion Port (Port A)

2.5External Memory Expansion Port (Port A)

When the DSP56301 enters a low-power standby mode (stop or wait), it releases bus mastership and tri-states the relevant Port A signals: A[0– 23], D[0– 23], AA0/RAS0– AA3/RAS3,

RD, WR, BB, CAS, BCLK, BCLK.

2.5.1External Address Bus

Table 2-6.External Address Bus Signals

Signal Name

Type

State During

Signal Description

Reset

 

 

 

 

 

 

 

 

 

 

 

A[0–23]

Output

Tri-stated

Address Bus—When the DSP is the bus master, A[0–23] are

 

 

 

active-high outputs that specify the address for external program

 

 

 

and data memory accesses. Otherwise, the signals are tri-stated.

 

 

 

To minimize power dissipation, A[0–23] do not change state

 

 

 

when external memory spaces are not being accessed.

 

 

 

 

2.5.2External Data Bus

.

Table 2-7.External Data Bus Signals

Signal Name

Type

State During

Signal Description

Reset

 

 

 

 

 

 

 

 

 

 

 

D[0–23]

Input/ Output

Tri-stated

Data Bus—When the DSP is the bus master, D0–D23 are

 

 

 

active-high, bidirectional input/outputs that provide the

 

 

 

bidirectional data bus for external program and data memory

 

 

 

accesses. Otherwise, D[0–23] are tri-stated. These lines have

 

 

 

weak keepers to maintain the last state even if all drivers are

 

 

 

tri-stated.

 

 

 

 

Notes: 1. One pin is reserved for use in the expansion port interface and the peripherals interface. Leave this pin unconnected.

2.5.3External Bus Control

 

 

 

 

Table 2-8.External Bus Control Signals

 

 

 

 

 

 

 

 

 

Signal

 

Type

State During

Signal Description

 

Name

 

Reset

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

AA[0–3]

 

Output

Tri-stated

Address Attribute—When defined as AA, these signals can be used as chip

 

 

 

 

 

selects or additional address lines. The default use defines a priority scheme

 

 

 

 

 

under which only one AA signal can be asserted at a time. Setting the AA priority

 

 

 

 

 

disable (APD) bit (Bit 14) of the OMR, the priority mechanism is disabled and the

 

 

 

 

 

lines can be used together as four external lines that can be decoded externally

 

 

 

 

 

into 16 chip select signals.

 

 

 

Output

Tri-stated

Row Address Strobe—When defined as

 

, these signals can be used as

 

RAS[0–3]

 

RAS

 

 

 

 

 

RAS for DRAM interface. These signals are tri-statable outputs with

 

 

 

 

 

programmable polarity.

 

 

 

 

 

 

 

 

2-6

DSP56301 User’s Manual

Page 35 Page 37
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Image 36
Motorola DSP56301 External Memory Expansion Port Port a, External Address Bus, External Data Bus, External Bus Control
Page 35 Page 37

DSP56301 specifications

The Motorola DSP56301 is a highly efficient digital signal processor, specifically engineered for real-time audio and speech processing applications. This DSP is part of Motorola's renowned DSP56300 family, which is recognized for its innovative features and outstanding performance in the realm of digital signal processing.

One of the main features of the DSP56301 is its ability to handle complex computations at high speeds. With a maximum clock frequency of 66 MHz, it delivers fast performance, enabling it to process audio signals in real time. The chip is built on a 24-bit architecture, which allows for high-resolution audio processing. This is particularly beneficial in applications such as telecommunications, consumer audio devices, and professional audio equipment, where precision is paramount.

The DSP56301 boasts a comprehensive instruction set that includes efficient mathematical operations, which are essential for digital filters and audio effects processing. One of the key innovations of this device is its dual data path architecture, which permits simultaneous processing of multiple data streams. This feature significantly enhances the device's throughput and responsiveness, making it suitable for demanding applications such as voice recognition and synthesis.

In terms of memory regions, the DSP56301 includes several on-chip memory categories, such as program memory, data memory, and a specialized memory for coefficients. The architecture's support for external memory expansion further increases its versatility, allowing designers to tailor systems to their specific requirements.

The DSP56301 implements advanced features such as a powerful on-chip hardware multiplier and accumulator, simplifying complex mathematical tasks and accelerating the execution of algorithms. Its flexible interrupt system enhances its capability to respond to time-sensitive operations, while the integrated serial ports facilitate efficient data communication with external devices.

Power consumption is also a vital characteristic of the DSP56301. It is designed with energy efficiency in mind, allowing for extended operation in battery-powered devices. The chip’s low power requirements are particularly advantageous in portable audio devices and other applications where energy conservation is crucial.

In conclusion, the Motorola DSP56301 is an exceptional digital signal processor that combines high processing power, flexibility, and efficiency. Its main features, advanced technologies, and robust architecture make it a top choice for developers seeking to create sophisticated audio and signal processing systems. With its enduring legacy in the industry, the DSP56301 continues to be relevant in a variety of modern applications, ensuring it remains a valuable tool for engineers and designers.
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