Host-Side Programming Model

Table 6-22.Host Interface Control Register (HCTR) Bit Definitions (Continued)

Bit

Bit Name

Reset

Mode

Description

Number

Value

 

 

 

 

 

 

 

 

 

 

 

 

 

9–8

HTF[1–0]

0

UBM

Host Transmit Data Transfer Format

 

 

 

PCI

Define data transfer formats for host-to-DSP communication. The data

 

 

 

 

transfer format converter (HDTFC) operates according to the specified

 

 

 

 

HTF[1–0] (see Table Table 6-4,Transmit Data Transfer Format, on

 

 

 

 

page 6-9). The personal hardware reset clears HTF[1–0].

 

 

 

 

PCI host-t- DSP data transfer formats (DCTR[HM] = $1):

 

 

 

 

ν If HCTR[HTF] = $0 (32-bit data mode):

 

 

 

 

All four PCI data bytes from HAD[31–0] pins are written to the

 

 

 

 

32-bit HTXR. The two least significant bytes are transferred to the

 

 

 

 

two least significant bytes of the DRXR FIFO. Then the two most

 

 

 

 

significant bytes are transferred to the two least significant bytes of

 

 

 

 

the DRXR FIFO. Thus, when the DSP56300 core reads two words

 

 

 

 

from the DRXR, the two least significant bytes of the first word read

 

 

 

 

contain the two least significant bytes of the 32-bit word written to

 

 

 

 

the HTXR, the two least significant bytes of the second word read

 

 

 

 

contain the two most significant bytes of the 32-bit word.

 

 

 

 

ν If HCTR[HTF] = $1 or $2:

 

 

 

 

The three least significant PCI data bytes from the HAD[23–0] pins

 

 

 

 

transfer to the three least significant HTXR bytes and are sent to

 

 

 

 

DRXR to be read by the DSP56300 core.

 

 

 

 

ν If HCTR[HTF] = $3:

 

 

 

 

The three most significant PCI data bytes from the HAD[31–8] pins

 

 

 

 

transfer to the three least significant HTXR bytes and are sent to

 

 

 

 

the DRXR to be read by the DSP56300 core.

Universal Bus mode host-to-DSP data transfer formats (DCTR[HM] = $2 or $3):

νIf HCTR[HTF] = $0:

The 24-bit data from HD[23–0] data pins transfers to the three least significant HTXR bytes and is sent to DRXR to be read by the DSP56300 core.

νIf HCTR[HTF] = $1:

The 16-bit data from HD[15–0] data pins transfers to the three least significant HTXR bytes as right aligned and zero extended and sent to DRXR to be read by the DSP56300 core.

νIf HCTR[HTF] = $2:

The 16-bit data from HD[15–0] data pins transfers to the three least significant HTXR bytes as right aligned and sign extended and sent to DRXR to be read by the DSP56300 core.

νIf HCTR[HTF] = $3:

The 16-bit data from HD[15–0] data pins transfers to the three least significant bytes of the HTXR as left aligned. The least significant byte is zero filled and sent to DRXR to be read by the DSP56300 core.

To assure proper operation:

νHTF[1–0] can be changed if the host-to-DSP data path is empty.

νSwitching between 32-bit data modes and non-32-bit data modes can occur only in the personal software reset state (DCTR[HM] = $0 and HACT = 0).

νIf the HTF[1–0] value is not equal to the value of the FC[1–0] bits in the DPMC, PCI transactions that start in the non-data address space (the PCI address is less than HI32_base_address:$007) should not extend into the data address space.

Host Interface (HI32)

6-51

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Motorola DSP56301 user manual Host Transmit Data Transfer Format
Page 168 Page 170

DSP56301 specifications

The Motorola DSP56301 is a highly efficient digital signal processor, specifically engineered for real-time audio and speech processing applications. This DSP is part of Motorola's renowned DSP56300 family, which is recognized for its innovative features and outstanding performance in the realm of digital signal processing.

One of the main features of the DSP56301 is its ability to handle complex computations at high speeds. With a maximum clock frequency of 66 MHz, it delivers fast performance, enabling it to process audio signals in real time. The chip is built on a 24-bit architecture, which allows for high-resolution audio processing. This is particularly beneficial in applications such as telecommunications, consumer audio devices, and professional audio equipment, where precision is paramount.

The DSP56301 boasts a comprehensive instruction set that includes efficient mathematical operations, which are essential for digital filters and audio effects processing. One of the key innovations of this device is its dual data path architecture, which permits simultaneous processing of multiple data streams. This feature significantly enhances the device's throughput and responsiveness, making it suitable for demanding applications such as voice recognition and synthesis.

In terms of memory regions, the DSP56301 includes several on-chip memory categories, such as program memory, data memory, and a specialized memory for coefficients. The architecture's support for external memory expansion further increases its versatility, allowing designers to tailor systems to their specific requirements.

The DSP56301 implements advanced features such as a powerful on-chip hardware multiplier and accumulator, simplifying complex mathematical tasks and accelerating the execution of algorithms. Its flexible interrupt system enhances its capability to respond to time-sensitive operations, while the integrated serial ports facilitate efficient data communication with external devices.

Power consumption is also a vital characteristic of the DSP56301. It is designed with energy efficiency in mind, allowing for extended operation in battery-powered devices. The chip’s low power requirements are particularly advantageous in portable audio devices and other applications where energy conservation is crucial.

In conclusion, the Motorola DSP56301 is an exceptional digital signal processor that combines high processing power, flexibility, and efficiency. Its main features, advanced technologies, and robust architecture make it a top choice for developers seeking to create sophisticated audio and signal processing systems. With its enduring legacy in the industry, the DSP56301 continues to be relevant in a variety of modern applications, ensuring it remains a valuable tool for engineers and designers.
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