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Motorola DSP56301 user manual Hbs

Models: DSP56301

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; Host boot program verify that the HI32 is operational by reading

;the status register (HSTR) and confirming that its value is $3.

;Suggested DSP-to-DSP connection:

;

 

 

 

 

 

;

slave

 

master

 

;

56301/HI32

 

563xx/PortA

 

;

 

 

 

 

 

;

HA[10:3]

<-

A[10:3]

; selects HI32 (base address 00000000)

;

HA[2:0]

<-

A[2:0]

; selects HTXR registers

;

HD[24:0]

<->

D[24:0]

; Data bus

;

HBS_

<-

BS_

; Bus Strobe (optional, see Note1)

;

HAEN

<-

AAx

; DMA cycle disable (AAx is active low)

;

HTA

 

->

TA_

; Transfer Acknowledge (optional, see Note2)

;

HIRQ_

->

IRQx_

; Interrupt Request (active low, open drain)

;

HWR_

<-

WR_

; Write strobe

;

HRD_

<-

RD_

; Read strobe

;

HRST

<-

system reset

; Reset (active low)

;

 

 

 

 

 

; Pins

HP31,

HP32 and HDAK_

must be tied to Vcc. Pins HP[22:20] can be

; used

as GPIO pins. Pin HINTA_ can be used as software driven interrupt

;request pin.

; Note1:

If HBS_ to BS_ connection is used,

the synchronous

connection of

; the HI32 is used

and therefore

the 563xx/master

should

access

the

; 56301/slave

as SRAM with 2 wait states.

In addition the

CLKOUT

of

; 563xx/master

should connect to

EXTAL

of 56301/slave, and

both

 

; master

and

slave

should

enable

the

PLL. For the slave

 

 

 

; multiplication, division

and

predivision

fuctors

should

be one

to

;guarantee syncronization between master and slave.

;For asynchronous connection, HBS_ must be tied to Vcc.

; Note2: If HTA to HTA_ connection is not

used, it is recommended that

; the HOST

Processor’s boot program verify

that the Host Interface

; is ready

by reading the status register (HSTR) and confirming that TRDY=1

;or HTRQ=1.

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

;If MD:MC:MB:MA=x100, then it loads the program RAM from the Host

;Interface programmed to operate in the PCI target (slave) mode.

;

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

; The HI32

bootstrap

code expects

first

to read a 24-bit

word specifying

; the number of program

words,

then a 24-bit word

specifying

the

 

 

; address to start loading

the program

words, and then

24-bit

word

for

; each

program

word

to be loaded.

 

 

 

 

 

 

 

 

 

;

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

; The

program

words

will

be

stored

in contiguous

PRAM

memory

; locations

starting

at

the

specified

starting

address.

After

; the

program

words are

read,

program

execution

starts

from

the

same

;address where loading started.

;

The Host Interface

bootstrap load program

can be stopped by setting the

;

Host Flag 0 (HF0)

in the HCTR register.

This starts execution of the

;loaded program from the specified starting address.

; The HOST

Processor

must first

configure the Host Interface

as

a PCI slave

; and then

start writing

data

to the Host

Interface.

The HOST

Processor

; must program the

HCTR

HTF1-HTF0 bits

as 01, 10

or

11

and then

 

 

 

 

 

 

 

 

 

DSP56301 User’s Manual

A-3

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Motorola DSP56301 user manual Hbs
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DSP56301 specifications

The Motorola DSP56301 is a highly efficient digital signal processor, specifically engineered for real-time audio and speech processing applications. This DSP is part of Motorola's renowned DSP56300 family, which is recognized for its innovative features and outstanding performance in the realm of digital signal processing.

One of the main features of the DSP56301 is its ability to handle complex computations at high speeds. With a maximum clock frequency of 66 MHz, it delivers fast performance, enabling it to process audio signals in real time. The chip is built on a 24-bit architecture, which allows for high-resolution audio processing. This is particularly beneficial in applications such as telecommunications, consumer audio devices, and professional audio equipment, where precision is paramount.

The DSP56301 boasts a comprehensive instruction set that includes efficient mathematical operations, which are essential for digital filters and audio effects processing. One of the key innovations of this device is its dual data path architecture, which permits simultaneous processing of multiple data streams. This feature significantly enhances the device's throughput and responsiveness, making it suitable for demanding applications such as voice recognition and synthesis.

In terms of memory regions, the DSP56301 includes several on-chip memory categories, such as program memory, data memory, and a specialized memory for coefficients. The architecture's support for external memory expansion further increases its versatility, allowing designers to tailor systems to their specific requirements.

The DSP56301 implements advanced features such as a powerful on-chip hardware multiplier and accumulator, simplifying complex mathematical tasks and accelerating the execution of algorithms. Its flexible interrupt system enhances its capability to respond to time-sensitive operations, while the integrated serial ports facilitate efficient data communication with external devices.

Power consumption is also a vital characteristic of the DSP56301. It is designed with energy efficiency in mind, allowing for extended operation in battery-powered devices. The chip’s low power requirements are particularly advantageous in portable audio devices and other applications where energy conservation is crucial.

In conclusion, the Motorola DSP56301 is an exceptional digital signal processor that combines high processing power, flexibility, and efficiency. Its main features, advanced technologies, and robust architecture make it a top choice for developers seeking to create sophisticated audio and signal processing systems. With its enduring legacy in the industry, the DSP56301 continues to be relevant in a variety of modern applications, ensuring it remains a valuable tool for engineers and designers.