Detected Parity Error, Bit, Devsel Timing, Bits

Programming Sheets

Application:			Date:
Application:			Date:
			Programmer:

Sheet 7 of 10

Host Processor (HI32)

Detected Parity Error, Bit 31

0 = No parity error detected

1 = Parity error detected Modes: PCI only

Signaled System Error, Bit 30

0 = No signaled system error detected

1 = Signaled system error detected Modes: PCI only

Received Master Abort, Bit 29

0 = No master abort received

1 = Master abort bus state Modes: PCI only

Received Target Abort, Bit 28

0 = No target abort received

1 = Target abort received Modes: PCI only

Signalled Target Abort, Bit 27

0 = No target abort issued (HI32 as target)

1 = HI32 issued target abort to terminate transaction Modes: PCI only

DEVSEL Timing, Bits 26–25

Always $1 (hardwired)

HI32 is medium DEVSEL timing class

Modes: PCI only

Data Parity Reported, Bit 24

0 = No parity error reported

1 = HI32 (as master) reported data parity error Modes: PCI only

Fast Back-to-Back Capable, Bit 23

Always 1 (hardwired)

Modes: PCI only

System Error Enable, Bit 8

0 = HSERR pin disabled

1 = HSERR pin enabled Modes: PCI only

Write Cycle Control, Bit 7

Always 0 (hardwired)

Modes: PCI only

Parity Error Response, Bit 6

0 = HI32 does not drive HPERR

1 = HPERR enabled for driving or detection Modes: PCI only

Bus Master Enable, Bit 2

0 = HI32 bus mastership disabled

1 = HI32 bus mastership enabled Modes: PCI only

Memory Space Enable, Bit 1

0 = Memory space response disabled

1 = Memory space response enabled Modes: PCI only

31 30 29 28					27 26 25 24				23 22 21 20				19 18 17 16				15 14 13 12				11 10		9	8	7	6	5	4	3	2	1	0
31 30 29 28					27 26 25 24				23 22 21 20				19 18 17 16				15 14 13 12				11 10		9	8	7	6	5	4	3	2	1	0
	DPE	SSE	RMA	RTA	STA	0	1	DPR	1	*0	*0	*0	*0	*0	*0	*0	*0	*0	*0	*0	*0	*0	*0	SERE	0	PERR	*0	*0	*0	BM	MSE	*0
	DPE	SSE	RMA	RTA	STA	DST1	DST0	DPR	FBBC															SERE	WCC	PERR				BM	MSE


	HI32 Status/Command Configuration Register (CSTR/CCMR)																					Read/Write
	Reset = $02400000																							* = Reserved, Program as 0
																								* = Reserved, Program as 0

Figure B-16.Status/Command Configuration Register (CSTR/CCMR)

B-28	DSP56301 User’s Manual

DSP56301 specifications

The Motorola DSP56301 is a highly efficient digital signal processor, specifically engineered for real-time audio and speech processing applications. This DSP is part of Motorola's renowned DSP56300 family, which is recognized for its innovative features and outstanding performance in the realm of digital signal processing.

One of the main features of the DSP56301 is its ability to handle complex computations at high speeds. With a maximum clock frequency of 66 MHz, it delivers fast performance, enabling it to process audio signals in real time. The chip is built on a 24-bit architecture, which allows for high-resolution audio processing. This is particularly beneficial in applications such as telecommunications, consumer audio devices, and professional audio equipment, where precision is paramount.

The DSP56301 boasts a comprehensive instruction set that includes efficient mathematical operations, which are essential for digital filters and audio effects processing. One of the key innovations of this device is its dual data path architecture, which permits simultaneous processing of multiple data streams. This feature significantly enhances the device's throughput and responsiveness, making it suitable for demanding applications such as voice recognition and synthesis.

In terms of memory regions, the DSP56301 includes several on-chip memory categories, such as program memory, data memory, and a specialized memory for coefficients. The architecture's support for external memory expansion further increases its versatility, allowing designers to tailor systems to their specific requirements.

The DSP56301 implements advanced features such as a powerful on-chip hardware multiplier and accumulator, simplifying complex mathematical tasks and accelerating the execution of algorithms. Its flexible interrupt system enhances its capability to respond to time-sensitive operations, while the integrated serial ports facilitate efficient data communication with external devices.

Power consumption is also a vital characteristic of the DSP56301. It is designed with energy efficiency in mind, allowing for extended operation in battery-powered devices. The chip’s low power requirements are particularly advantageous in portable audio devices and other applications where energy conservation is crucial.

In conclusion, the Motorola DSP56301 is an exceptional digital signal processor that combines high processing power, flexibility, and efficiency. Its main features, advanced technologies, and robust architecture make it a top choice for developers seeking to create sophisticated audio and signal processing systems. With its enduring legacy in the industry, the DSP56301 continues to be relevant in a variety of modern applications, ensuring it remains a valuable tool for engineers and designers.

Motorola DSP56301 Detected Parity Error, Bit, Signaled System Error, Bit, Devsel Timing, Bits

Models: DSP56301

Host Processor (HI32)

Detected Parity Error, Bit 31

Signaled System Error, Bit 30

Received Master Abort, Bit 29

Received Target Abort, Bit 28

Signalled Target Abort, Bit 27

DEVSEL Timing, Bits 26–25

Data Parity Reported, Bit 24

Fast Back-to-Back Capable, Bit 23

System Error Enable, Bit 8

Write Cycle Control, Bit 7

Parity Error Response, Bit 6

Bus Master Enable, Bit 2

Memory Space Enable, Bit 1

Figure B-16.Status/Command Configuration Register (CSTR/CCMR)

DSP56301 specifications