Bit Counter, Divide by, CD11-0 | Motorola DSP56301 instruction

SCI Programming Model

Table 8-5.SCI Clock Control Register (SCCR) Bit Definitions (Continued)

Bit	Bit Name	Reset	Description
Number	Bit Name	Value	Description


11–0	CD[11–0]	0	Clock Divider
			Specifies the divide ratio of the prescale divider in the SCI clock generator. A divide
			ratio from 1 to 4096 (CD[11–0] = $000 to $FFF) can be selected.

The SCI clock determines the data transmission (baud) rate and can also establish a periodic interrupt that can act as an event timer or be used in any other timing function. Bits CD11– CD0, SCP, and SCR[STIR] work together to determine the time base. If SCR[TMIE] = 1 when the periodic time-out occurs, the SCI timer interrupt is recognized and pending. The SCI timer interrupt is automatically cleared when the interrupt is serviced. This interrupt occurs every time the periodic timer times out.

Figure 8-5shows the block diagram of the internal clock generation circuitry with the formula to compute the bit rate when the internal clock is used.

Fcore

Divide	12-bit Counter	Prescaler:	Divide
Divide		Divide by	Divide
By 2			By 2
By 2			By 2
		1 or 8
	CD[11–0]	SCP
	CD[11–0]
			Internal Clock

STIR

Divide by 16

Timer Interrupt (STMINT)

SCI Core Logic

Uses Divide by 16 for

Asynchronous

Uses Divide by 2 for

Synchronous

COD

If Asynchronous Divide by 1 or 16 If Synchronous Divide By 2

	Fcore	SCKP
bps = 64 × (7(SCP) + 1) × CD + 1)		SCKP
bps = 64 × (7(SCP) + 1) × CD + 1)

where: SCP = 0 or 1

CD = $000 to $FFF

Figure 8-5.SCI Baud Rate Generator

SCKP = 0 + SCKP = 1 -

SCLK

8-20	DSP56301 User’s Manual

DSP56301 specifications

The Motorola DSP56301 is a highly efficient digital signal processor, specifically engineered for real-time audio and speech processing applications. This DSP is part of Motorola's renowned DSP56300 family, which is recognized for its innovative features and outstanding performance in the realm of digital signal processing.

One of the main features of the DSP56301 is its ability to handle complex computations at high speeds. With a maximum clock frequency of 66 MHz, it delivers fast performance, enabling it to process audio signals in real time. The chip is built on a 24-bit architecture, which allows for high-resolution audio processing. This is particularly beneficial in applications such as telecommunications, consumer audio devices, and professional audio equipment, where precision is paramount.

The DSP56301 boasts a comprehensive instruction set that includes efficient mathematical operations, which are essential for digital filters and audio effects processing. One of the key innovations of this device is its dual data path architecture, which permits simultaneous processing of multiple data streams. This feature significantly enhances the device's throughput and responsiveness, making it suitable for demanding applications such as voice recognition and synthesis.

In terms of memory regions, the DSP56301 includes several on-chip memory categories, such as program memory, data memory, and a specialized memory for coefficients. The architecture's support for external memory expansion further increases its versatility, allowing designers to tailor systems to their specific requirements.

The DSP56301 implements advanced features such as a powerful on-chip hardware multiplier and accumulator, simplifying complex mathematical tasks and accelerating the execution of algorithms. Its flexible interrupt system enhances its capability to respond to time-sensitive operations, while the integrated serial ports facilitate efficient data communication with external devices.

Power consumption is also a vital characteristic of the DSP56301. It is designed with energy efficiency in mind, allowing for extended operation in battery-powered devices. The chip’s low power requirements are particularly advantageous in portable audio devices and other applications where energy conservation is crucial.

In conclusion, the Motorola DSP56301 is an exceptional digital signal processor that combines high processing power, flexibility, and efficiency. Its main features, advanced technologies, and robust architecture make it a top choice for developers seeking to create sophisticated audio and signal processing systems. With its enduring legacy in the industry, the DSP56301 continues to be relevant in a variety of modern applications, ensuring it remains a valuable tool for engineers and designers.

Motorola DSP56301 user manual Bit Counter, Divide by, CD11-0, Sckp = 0 + Sckp =

Models: DSP56301

11–0

Figure 8-5shows the block diagram of the internal clock generation circuitry with the formula to compute the bit rate when the internal clock is used.

12-bit Counter

Divide by

CD[11–0]

Figure 8-5.SCI Baud Rate Generator

SCKP = 0 + SCKP = 1 -

SCLK

DSP56301 specifications