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Motorola DSP56301 user manual Host Transmit Data Register Htxr

Models: DSP56301

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Host-Side Programming Model

the pins and their alignment. (See Section 6.3.2, DSP-To-Host Data Path, on page 6-7and Section 6.3.1, Host-to-DSP Data Path, on page 6-6).

In a PCI mode (DCTR[HM] = $1) memory space read transaction, the HRXS is accessed if the PCI address is between HI32_base_address: $01C and HI32_base_address: $FFFC. The host processor views HRXS as a 16377 Dword read-only memory. In PCI DSP-to-host data transfers via the HRXS, all four byte lanes are driven with data, in accordance with HRF[1–0] bits, regardless of the value of the byte enable pins (HC3/HBE3-HC0/HBE0).

In a Universal Bus mode (DCTR[HM] = $2 or $3), the HRXS is accessed if the HA[10–3]value matches the HI32 base address (CBMA, see Section 6.8.11, Memory Space Base Address Configuration Register (CBMA), on page 6-70)and the HA[2–0]value is $7. In a

24-bit data Universal Bus mode (DCTR[HM] = $2 or $3 and HCTR[HRF] = $0), the HRXS is viewed by the host processor as a 24-bit read-only register. HD[23–0]pins are driven with all three bytes of the HRXS in a read access. In a 16-bit data Universal Bus mode (DCTR[HM] = $2 or $3 and HCTR[HRF]≠$0), the HRXS is viewed by the host processor as a 16-bit read-only register. In a read access, the HD[15–0]pins are driven with data from the two most significant bytes or two least significant bytes of the HRXS, as defined by the HCTR[HRF] bits. When HSTR[HRRQ] is set and HCTR[RREQ] is set:

νThe HREQ status bit is set in the HSTR.

νThe HIRQ pin is asserted, if DMAE is cleared (in the Universal Bus modes).

νThe HDRQ pin is asserted, if DMAE is set (in the Universal Bus modes).

If TWSD is cleared, the HI32, as the selected PCI target (DCTR[HM] = $1) in a read data phase from the HRXS inserts PCI wait states if the HRXS is empty (HRRQ = 0). Wait states are inserted until the data is transferred from the DSP side to the HRXS. Up to eight wait states can be inserted before a target-initiated transaction termination (disconnect-C/Retry) is generated.

In a Universal Bus mode read from the HRXS, the HI32 inserts wait states if the HRXS is empty (HRRQ = 0). Wait states are inserted until the data transfers from the DSP side to the HRXS. Hardware, software and personal software resets empty the HRXS (HSTR[HRRQ] is cleared).

6.8.6Host Transmit Data Register (HTXR)

The HTXR is the input stage of the host-to-DSP data path FIFO for host-to-DSP data transfers. The DSP56300 core cannot access HTXR. The host processor can write to the HTXR if the HSTR[HTRQ] bit is set. Data should not be written to the HTXR until HSTR[HTRQ] is set to prevent previous data from being overwritten. Filling the HTXR by host processor writes clears HSTR[HTRQ].

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DSP56301 User’s Manual

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Motorola DSP56301 user manual Host Transmit Data Register Htxr
Page 179 Page 181

DSP56301 specifications

The Motorola DSP56301 is a highly efficient digital signal processor, specifically engineered for real-time audio and speech processing applications. This DSP is part of Motorola's renowned DSP56300 family, which is recognized for its innovative features and outstanding performance in the realm of digital signal processing.

One of the main features of the DSP56301 is its ability to handle complex computations at high speeds. With a maximum clock frequency of 66 MHz, it delivers fast performance, enabling it to process audio signals in real time. The chip is built on a 24-bit architecture, which allows for high-resolution audio processing. This is particularly beneficial in applications such as telecommunications, consumer audio devices, and professional audio equipment, where precision is paramount.

The DSP56301 boasts a comprehensive instruction set that includes efficient mathematical operations, which are essential for digital filters and audio effects processing. One of the key innovations of this device is its dual data path architecture, which permits simultaneous processing of multiple data streams. This feature significantly enhances the device's throughput and responsiveness, making it suitable for demanding applications such as voice recognition and synthesis.

In terms of memory regions, the DSP56301 includes several on-chip memory categories, such as program memory, data memory, and a specialized memory for coefficients. The architecture's support for external memory expansion further increases its versatility, allowing designers to tailor systems to their specific requirements.

The DSP56301 implements advanced features such as a powerful on-chip hardware multiplier and accumulator, simplifying complex mathematical tasks and accelerating the execution of algorithms. Its flexible interrupt system enhances its capability to respond to time-sensitive operations, while the integrated serial ports facilitate efficient data communication with external devices.

Power consumption is also a vital characteristic of the DSP56301. It is designed with energy efficiency in mind, allowing for extended operation in battery-powered devices. The chip’s low power requirements are particularly advantageous in portable audio devices and other applications where energy conservation is crucial.

In conclusion, the Motorola DSP56301 is an exceptional digital signal processor that combines high processing power, flexibility, and efficiency. Its main features, advanced technologies, and robust architecture make it a top choice for developers seeking to create sophisticated audio and signal processing systems. With its enduring legacy in the industry, the DSP56301 continues to be relevant in a variety of modern applications, ensuring it remains a valuable tool for engineers and designers.