Treq, Dmae, Isa/Eisa, Sft, Pci Ubm, Twsd, Htrq

HI32 Programming Model/Quick Reference

HI32 Registers—Quick Reference

Reg			Bit								Comments	Reset Type

	Num	Mnemonic	Name	Val			Function					HS	PH	PS
	Num	Mnemonic	Name	Val			Function					HS	PH	PS

					Host Side

HCTR	1	TREQ	Transmit Request	0		HTRQ interrupt disabled						-	0	-
	1		Enable	1		HTRQ interrupt enabled
			Enable	1		HTRQ interrupt enabled
	2	RREQ	Receive Request	0		HRRQ interrupt disabled						-	0	-
	2		Enable	1		HRRQ interrupt enabled
			Enable	1		HRRQ interrupt enabled
	5-3	HF[2–0]	Host Flags									-	0	-
		DMAE	DMA Enable	0		HI32 does not support DMA						-	0	-
	6		(ISA/EISA)	1		transfers
	6					HI32 supports ISA-DMA type
						HI32 supports ISA-DMA type
						transfers
	7	SFT	Slave Fetch Type	0		Pre-fetch						-	0	-
	7			1		Fetch
				1		Fetch
		HTF[1–0]	Host Transmit Data			PCI				UBM		-	$0	-
			Transfer Format	00		32-bit mode			24-bit mode
	9-8			01		3 LSBs		2 Right, zero ext.
				10		3 LSBs		2 Right, sign ext.
				11		3 MSbs			2 Left, zero filled
		HRF[1–0]	Host Receive Data			PCI				UBM		-	$0	-
			Transfer Format	00		32-bit mode			24-bit mode
	12-11			01		3 Right, zero ext.				2 LSBs
	12-11			10		3 Right, sign ext.				2 LSBs
				10		3 Right, sign ext.				2 LSBs
				11		3 Left, zero filled				2 middle
										bytes
	16-14	HS[2–0]	Host Semaphores									-	0	-
		TWSD	Target Wait State	0		HI32 target inserts up to 8						-	0	-
	19		Disable			wait states
	19			1		HI32 target does not insert
				1		HI32 target does not insert
						wait states
HSTR		TRDY	Transmitter Ready	1		transmit FIF O (6 deep) is						1	-	1
	0					empty
				0		transmit FIFO is not empty
	1	HTRQ	Host Transmit Data	1		host transmit FIFO is not full						1	-	1
	1		Request	0		host transmit FIFO is full
			Request	0		host transmit FIFO is full
		HRRQ	Host Receive Data	0		host receive FIFO is empty						0	-	0
	2		Request	1		host receive FIFO is not
						empty
	5-3	HF[5–3]	Host Flags									0	-	-
	6	HINT	Host Interrupt A	0		HINTA pin is high impedance						0	-	-
	6			1		HINTA pin is driven low
				1		HINTA pin is driven low
		HREQ	Host Request	0			pin is deasserted					-	0	-
		HREQ	Host Request	0		HIRQ	pin is deasserted					-	0	-
	7			1		HIRQ pin is asserted (if
						enabled)

6-78	DSP56301 User’s Manual

DSP56301 specifications

The Motorola DSP56301 is a highly efficient digital signal processor, specifically engineered for real-time audio and speech processing applications. This DSP is part of Motorola's renowned DSP56300 family, which is recognized for its innovative features and outstanding performance in the realm of digital signal processing.

One of the main features of the DSP56301 is its ability to handle complex computations at high speeds. With a maximum clock frequency of 66 MHz, it delivers fast performance, enabling it to process audio signals in real time. The chip is built on a 24-bit architecture, which allows for high-resolution audio processing. This is particularly beneficial in applications such as telecommunications, consumer audio devices, and professional audio equipment, where precision is paramount.

The DSP56301 boasts a comprehensive instruction set that includes efficient mathematical operations, which are essential for digital filters and audio effects processing. One of the key innovations of this device is its dual data path architecture, which permits simultaneous processing of multiple data streams. This feature significantly enhances the device's throughput and responsiveness, making it suitable for demanding applications such as voice recognition and synthesis.

In terms of memory regions, the DSP56301 includes several on-chip memory categories, such as program memory, data memory, and a specialized memory for coefficients. The architecture's support for external memory expansion further increases its versatility, allowing designers to tailor systems to their specific requirements.

The DSP56301 implements advanced features such as a powerful on-chip hardware multiplier and accumulator, simplifying complex mathematical tasks and accelerating the execution of algorithms. Its flexible interrupt system enhances its capability to respond to time-sensitive operations, while the integrated serial ports facilitate efficient data communication with external devices.

Power consumption is also a vital characteristic of the DSP56301. It is designed with energy efficiency in mind, allowing for extended operation in battery-powered devices. The chip’s low power requirements are particularly advantageous in portable audio devices and other applications where energy conservation is crucial.

In conclusion, the Motorola DSP56301 is an exceptional digital signal processor that combines high processing power, flexibility, and efficiency. Its main features, advanced technologies, and robust architecture make it a top choice for developers seeking to create sophisticated audio and signal processing systems. With its enduring legacy in the industry, the DSP56301 continues to be relevant in a variety of modern applications, ensuring it remains a valuable tool for engineers and designers.

Motorola DSP56301 user manual Treq, Dmae, Isa/Eisa, Sft, Pci Ubm, Twsd, Hstr Trdy, Htrq, Hrrq

Models: DSP56301

TREQ

DMAE

(ISA/EISA)

SFT

PCI

UBM

TWSD

HSTR

TRDY

HTRQ

HRRQ

HIRQ

DSP56301 specifications