Timer Toggle Mode, Toggle Timer | Motorola DSP56301 specification

Operating Modes

9.3.1.3 Timer Toggle (Mode 2)

	Bit Settings					Mode Characteristics

TC3	TC2	TC1	TC0	Mode	Name		Function	TIO	Clock


0	0	1	0	2	Toggle		Timer	Output	Internal

In Mode 2, the timer periodically toggles the polarity of the TIO signal. When the timer is enabled, the TIO signal is loaded with the value of the TCSR[INV] bit. When the counter value matches the value in the TCPR, the polarity of the TIO output signal is inverted.

TCSR[TCF] is set, and a compare interrupt is generated if the TCSR[TCIE] bit is set. If the TCSR[TRM] bit is set, the counter is loaded with the value of the TLR when the next timer clock is received, and the count resumes. If the TRM bit is cleared, the counter continues to increment on each timer clock. This process repeats until the timer is cleared (disabling the timer). The TCPR[TLR] value sets the delay between starting the timer and toggling the TIO signal. To generate output signals with a delay of X clock cycles between toggles, set the TLR value to X/2, and set the TCSR[TRM] bit. This process repeats until the timer is disabled (that is, TCSR[TE] is cleared).

Mode 2 (internal clock): TRM = 1 first event

N = write preload

M = write compare

TE
Clock
(CLK/2 or prescale CLK)
TLR	N
Counter (TCR)	0	N	N + 1	M	N	N + 1
TCPR	M

TCF (Compare Interrupt if TCIE = 1)

TIO pin (INV = 0)				pulse width =
				pulse width =
				M - N clock
TIO pin (INV = 1)				periods
TIO pin (INV = 1)

Figure 9-7.Toggle Mode, TRM = 1

9-10	DSP56301 User’s Manual

DSP56301 specifications

The Motorola DSP56301 is a highly efficient digital signal processor, specifically engineered for real-time audio and speech processing applications. This DSP is part of Motorola's renowned DSP56300 family, which is recognized for its innovative features and outstanding performance in the realm of digital signal processing.

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In terms of memory regions, the DSP56301 includes several on-chip memory categories, such as program memory, data memory, and a specialized memory for coefficients. The architecture's support for external memory expansion further increases its versatility, allowing designers to tailor systems to their specific requirements.

The DSP56301 implements advanced features such as a powerful on-chip hardware multiplier and accumulator, simplifying complex mathematical tasks and accelerating the execution of algorithms. Its flexible interrupt system enhances its capability to respond to time-sensitive operations, while the integrated serial ports facilitate efficient data communication with external devices.

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In conclusion, the Motorola DSP56301 is an exceptional digital signal processor that combines high processing power, flexibility, and efficiency. Its main features, advanced technologies, and robust architecture make it a top choice for developers seeking to create sophisticated audio and signal processing systems. With its enduring legacy in the industry, the DSP56301 continues to be relevant in a variety of modern applications, ensuring it remains a valuable tool for engineers and designers.

Motorola DSP56301 Timer Toggle Mode, Mode 2 internal clock TRM = 1 first event, Toggle Timer

Models: DSP56301

9.3.1.3 Timer Toggle (Mode 2)

TC3

TIO

Toggle

Timer

Output

Mode 2 (internal clock): TRM = 1 first event

N = write preload

M = write compare

Clock

(CLK/2 or prescale CLK)

TLR

Figure 9-7.Toggle Mode, TRM = 1

DSP56301 specifications