Operating Mode Register OMR | Motorola DSP56301 instruction

Central Processor Unit (CPU) Registers

4.3.2Operating Mode Register (OMR)

The OMR is a read/write register divided into three byte-sized units. The lowest two bytes (EOM and COM) control the chip’s operating mode. The high byte (SCS) controls and monitors the stack extension. The OMR control bits are shown in Figure 4-2.

	Stack Control/Status (SCS)							Extended Operating Mode (EOM)									Chip Operating Mode (COM)

23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			SEN	WRP	EOV	EUN	XYS	ATE	APD	ABE	BRT	TAS	BE	CDP[1–0]		MS	SD		EBD	MD	MC	MB	MA
Reset:
0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	1	0	0	0	0	*	*	*	*

*After reset, these bits reflect the corresponding value of the mode input (that is, MODD, MODC, MODB, or MODA, respectively).

Reserved bit. Read as zero; write to zero for future compatibility

Figure 4-2.Operating Mode Register (OMR)

The Enhanced Operating Mode (EOM) and Chip Operating Mode (COM) bytes are affected only by processor reset and by instructions directly referencing the OMR (that is, ANDI, ORI, and other instructions, such as MOVEC, that specify OMR as a destination). The Stack Control/Status (SCS) byte is referenced implicitly by some instructions, such as DO, JSR, and RTI, or directly by the MOVEC instruction. During processor reset, the chip operating mode bits (MD, MC, MB, and MA) are loaded from the external mode select pins MODD–MODA, respectively. Table 4-4defines the DSP56301 OMR bits.

Table 4-4.Operating Mode Register (OMR) Bit Definitions

Bit Number	Bit Name	Reset Value	Description


23–21		0	Reserved. Write to 0 for future compatibility.

20	SEN	0	Stack Extension Enable
			Enables/disables the stack extension in data memory. If the SEN bit is set,
			the extension is enabled. Hardware reset clears this bit, so the default out
			of reset is a disabled stack extension.

19	WRP	0	Stack Extension Wrap Flag
			Set when copying from the on-chip hardware stack (System Stack
			Register file) to the stack extension memory begins. You can use this flag
			during the debugging phase of the software development to evaluate and
			increase the speed of software-implemented algorithms. The WRP flag is
			a sticky bit (that is, cleared only by hardware reset or by an explicit
			MOVEC operation to the OMR).

4-12	DSP56301 User’s Manual

DSP56301 specifications

The Motorola DSP56301 is a highly efficient digital signal processor, specifically engineered for real-time audio and speech processing applications. This DSP is part of Motorola's renowned DSP56300 family, which is recognized for its innovative features and outstanding performance in the realm of digital signal processing.

One of the main features of the DSP56301 is its ability to handle complex computations at high speeds. With a maximum clock frequency of 66 MHz, it delivers fast performance, enabling it to process audio signals in real time. The chip is built on a 24-bit architecture, which allows for high-resolution audio processing. This is particularly beneficial in applications such as telecommunications, consumer audio devices, and professional audio equipment, where precision is paramount.

The DSP56301 boasts a comprehensive instruction set that includes efficient mathematical operations, which are essential for digital filters and audio effects processing. One of the key innovations of this device is its dual data path architecture, which permits simultaneous processing of multiple data streams. This feature significantly enhances the device's throughput and responsiveness, making it suitable for demanding applications such as voice recognition and synthesis.

In terms of memory regions, the DSP56301 includes several on-chip memory categories, such as program memory, data memory, and a specialized memory for coefficients. The architecture's support for external memory expansion further increases its versatility, allowing designers to tailor systems to their specific requirements.

The DSP56301 implements advanced features such as a powerful on-chip hardware multiplier and accumulator, simplifying complex mathematical tasks and accelerating the execution of algorithms. Its flexible interrupt system enhances its capability to respond to time-sensitive operations, while the integrated serial ports facilitate efficient data communication with external devices.

Power consumption is also a vital characteristic of the DSP56301. It is designed with energy efficiency in mind, allowing for extended operation in battery-powered devices. The chip’s low power requirements are particularly advantageous in portable audio devices and other applications where energy conservation is crucial.

In conclusion, the Motorola DSP56301 is an exceptional digital signal processor that combines high processing power, flexibility, and efficiency. Its main features, advanced technologies, and robust architecture make it a top choice for developers seeking to create sophisticated audio and signal processing systems. With its enduring legacy in the industry, the DSP56301 continues to be relevant in a variety of modern applications, ensuring it remains a valuable tool for engineers and designers.

Motorola DSP56301 Operating Mode Register OMR Bit Definitions, Stack Extension Enable

Models: DSP56301

4.3.2Operating Mode Register (OMR)

Figure 4-2.Operating Mode Register (OMR)

Table 4-4.Operating Mode Register (OMR) Bit Definitions

Stack Extension Enable

Stack Extension Wrap Flag

DSP56301 specifications