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Motorola DSP56301 DSP Status Register DSR Bit Definitions, Mode Description Number Value

Models: DSP56301

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HI32 DSP-Side Programming Model

 

 

 

 

 

 

 

 

 

 

 

Table 6-14.DSP Status Register (DSR) Bit Definitions (Continued)

 

 

 

 

 

 

 

 

 

 

 

Bit

Bit Name

Reset

Mode

 

 

Description

 

 

Number

Value

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

STRQ

1

UBM

Slave Transmit Data Request

 

 

 

 

 

PCI

Indicates that the slave transmit data FIFO (DTXS) is not full and the

 

 

 

 

 

 

 

DSP56300 core can write to it. STRQ functions in accordance with the

 

 

 

 

 

 

 

value of the slave fetch type (SFT) bit in the Host Control Register

 

 

 

 

 

 

 

(HCTR). In Fetch mode, the HI32 requests data from the DSP56300

 

 

 

 

 

 

 

core (by enabling the STRQ status bit and generating core interrupt

 

 

 

 

 

 

 

requests or DMA requests, if enabled), only after the host begins a read

 

 

 

 

 

 

 

transaction from the HI32. In Pre-Fetch mode when the DTXS is not full,

 

 

 

 

 

 

 

the HI32 requests data from the DSP56300 core (by enabling the STRQ

 

 

 

 

 

 

 

status bit and generating core interrupt requests or DMA requests if

 

 

 

 

 

 

 

enabled). Hardware, software, and personal software resets set STRQ.

 

 

 

 

 

 

 

In the personal software reset state, STRQ = 0.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PCI mode (DCTR[HM] =

 

Fetch (SFT = 1): The DSP-to-host data path

 

 

 

 

 

 

 

$1)

 

is a six word deep FIFO buffer (three word

 

 

 

 

 

 

 

 

 

deep in the 32-bit data format mode,

 

 

 

 

 

 

 

 

 

HCTR[HRF] = $0). During a read transaction

 

 

 

 

 

 

 

 

 

from the DTXS-HRXS FIFO, STRQ reflects

 

 

 

 

 

 

 

 

 

the status of the DTXS. STRQ is set if the

 

 

 

 

 

 

 

 

 

DTXS is not full. STRQ is cleared when the

 

 

 

 

 

 

 

 

 

DSP56300 core fills the DTXS. When the

 

 

 

 

 

 

 

 

 

host is not executing a read transaction from

 

 

 

 

 

 

 

 

 

the HRXS, the DSP-to-host data path is

 

 

 

 

 

 

 

 

 

forced to the reset state and STRQ is

 

 

 

 

 

 

 

 

 

cleared.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Universal Bus mode

 

Fetch (SFT = 1): There is no FIFO buffering

 

 

 

 

 

 

 

(DCTR[HM] = $2 or $3)

 

of the DSP-to-host data path. At the

 

 

 

 

 

 

 

 

 

beginning of a read data transfer from the

 

 

 

 

 

 

 

 

 

HRXS, STRQ is set. STRQ is cleared when

 

 

 

 

 

 

 

 

 

the DSP56300 core writes to the DTXS. If the

 

 

 

 

 

 

 

 

 

host is not reading from the HRXS, the

 

 

 

 

 

 

 

 

 

DSP-to-host data path is forced to the reset

 

 

 

 

 

 

 

 

 

and STRQ is cleared.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PCI and Universal Bus

 

Pre-Fetch (SFT = 0): The DSP-to-host data

 

 

 

 

 

 

 

modes (DCTR[HM] = $1,

 

path is a six word deep FIFO buffer (three

 

 

 

 

 

 

 

$2 or $3)

 

word deep in the 32-bit data format mode,

 

 

 

 

 

 

 

 

 

DCTR[HM] = $1 and HCTR[HRF] = $0).

 

 

 

 

 

 

 

 

 

STRQ is set if the DTXS is not full. STRQ is

 

 

 

 

 

 

 

 

 

cleared when the DSP56300 core fills the

 

 

 

 

 

 

 

 

 

DTXS.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

STRQ is set

 

ν When STIE is set, a slave transmit

 

 

 

 

 

 

 

 

 

data interrupt request is generated.

 

 

 

 

 

 

 

 

 

ν When enabled by a DSP56300 core

 

 

 

 

 

 

 

 

 

DMA channel, a slave transmit data

 

 

 

 

 

 

 

 

 

DMA request is generated.

 

 

 

 

 

 

 

 

 

 

 

 

0

HCP

0

UBM

Host Command Pending

 

 

 

 

 

 

PCI

Indicates that the host has set the HC bit and that a host command

 

 

 

 

 

 

 

interrupt is pending. The HCP bit reflects the status of the HC bit in the

 

 

 

 

 

 

 

HCVR. If HCP is set and HCIE is set, a host command interrupt request

 

 

 

 

 

 

 

is generated. The HI32 interrupt logic hardware clears HC and HCP

 

 

 

 

 

 

 

when the HC interrupt request is serviced. The host cannot clear HC.

 

 

 

 

 

 

 

 

 

 

 

Host Interface (HI32)

6-37

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Motorola DSP56301 DSP Status Register DSR Bit Definitions, Mode Description Number Value, Slave Transmit Data Request
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DSP56301 specifications

The Motorola DSP56301 is a highly efficient digital signal processor, specifically engineered for real-time audio and speech processing applications. This DSP is part of Motorola's renowned DSP56300 family, which is recognized for its innovative features and outstanding performance in the realm of digital signal processing.

One of the main features of the DSP56301 is its ability to handle complex computations at high speeds. With a maximum clock frequency of 66 MHz, it delivers fast performance, enabling it to process audio signals in real time. The chip is built on a 24-bit architecture, which allows for high-resolution audio processing. This is particularly beneficial in applications such as telecommunications, consumer audio devices, and professional audio equipment, where precision is paramount.

The DSP56301 boasts a comprehensive instruction set that includes efficient mathematical operations, which are essential for digital filters and audio effects processing. One of the key innovations of this device is its dual data path architecture, which permits simultaneous processing of multiple data streams. This feature significantly enhances the device's throughput and responsiveness, making it suitable for demanding applications such as voice recognition and synthesis.

In terms of memory regions, the DSP56301 includes several on-chip memory categories, such as program memory, data memory, and a specialized memory for coefficients. The architecture's support for external memory expansion further increases its versatility, allowing designers to tailor systems to their specific requirements.

The DSP56301 implements advanced features such as a powerful on-chip hardware multiplier and accumulator, simplifying complex mathematical tasks and accelerating the execution of algorithms. Its flexible interrupt system enhances its capability to respond to time-sensitive operations, while the integrated serial ports facilitate efficient data communication with external devices.

Power consumption is also a vital characteristic of the DSP56301. It is designed with energy efficiency in mind, allowing for extended operation in battery-powered devices. The chip’s low power requirements are particularly advantageous in portable audio devices and other applications where energy conservation is crucial.

In conclusion, the Motorola DSP56301 is an exceptional digital signal processor that combines high processing power, flexibility, and efficiency. Its main features, advanced technologies, and robust architecture make it a top choice for developers seeking to create sophisticated audio and signal processing systems. With its enduring legacy in the industry, the DSP56301 continues to be relevant in a variety of modern applications, ensuring it remains a valuable tool for engineers and designers.