Operating Modes

9.3.2.2 Measurement Input Period (Mode 5)

 

Bit Settings

 

 

 

Mode Characteristics

 

 

 

 

 

 

 

 

 

 

 

 

TC3

TC2

TC1

TC0

Mode

Name

 

Function

TIO

Clock

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

1

0

1

5

Input period

 

Measurement

Input

Internal

In Mode 5, the timer counts the period between the reception of signal edges of the same polarity across the TIO signal. The value of the INV bit determines whether the period is measured between consecutive low-to-high (0 to 1) transitions of TIO or between consecutive high-to-low (1 to 0) transitions of TIO. If INV is set, high-to-low signal transitions are selected. If INV is cleared, low-to-high signal transitions are selected. After the first appropriate transition occurs on the TIO input signal, the counter is loaded with the TLR value. On the next signal transition of the same polarity that occurs on TIO, TCSR[TCF] is set, and a compare interrupt is generated if the TCSR[TCIE] bit is set. The contents of the counter load into the TCR. The TCR then contains the value of the time that elapsed between the two signal transitions on the TIO signal. After the second signal transition, if the TCSR[TRM] bit is set, the TCSR[TE] bit is set to clear the counter and enable the timer. The counter is repeatedly loaded and incremented until the timer is disabled. If the TCSR[TRM] bit is cleared, the counter continues to increment until it overflows.

Mode 5 (internal clock): TRM = 1

first event

 

 

 

N = write preload

 

 

 

 

 

M = write compare

 

 

 

 

 

TE

 

 

 

 

 

Clock

 

 

 

 

 

(CLK/2 or prescale CLK)

 

 

 

 

TLR

N

 

 

 

 

Counter

0

N

N + 1

M

N

TCR

 

 

 

 

M

TIO pin

 

period being measured

 

 

 

 

 

 

 

TCF (Compare Interrupt if TCIE = 1)

 

 

 

NOTE: If INV = 1, a 1-to-0 edge on TIO loads the counter, and a 0-to-1 edge on TIO loads TCR with count and the counter with N.

Counter continues counting,N +does1

not stop

Interrupt Service reads TCR; period

=M - N clock periods

Figure 9-13.Period Measurement Mode, TRM = 1

9-16

DSP56301 User’s Manual

Page 278
Image 278
Motorola DSP56301 Measurement Input Period Mode, Mode 5 internal clock TRM =, First event = write preload = write compare

DSP56301 specifications

The Motorola DSP56301 is a highly efficient digital signal processor, specifically engineered for real-time audio and speech processing applications. This DSP is part of Motorola's renowned DSP56300 family, which is recognized for its innovative features and outstanding performance in the realm of digital signal processing.

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In terms of memory regions, the DSP56301 includes several on-chip memory categories, such as program memory, data memory, and a specialized memory for coefficients. The architecture's support for external memory expansion further increases its versatility, allowing designers to tailor systems to their specific requirements.

The DSP56301 implements advanced features such as a powerful on-chip hardware multiplier and accumulator, simplifying complex mathematical tasks and accelerating the execution of algorithms. Its flexible interrupt system enhances its capability to respond to time-sensitive operations, while the integrated serial ports facilitate efficient data communication with external devices.

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