Motorola DSP56301 user manual DMA Control Registers DCR5-DCR0

Programming Sheets

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Sheet 1 of 1

DMA Channel Enable, Bit 23

Three-Dimensional Mode, Bit 10

DMA

0 = Disables channel operation

0 = Three-Dimensional mode disabled

1 = Enables channel operation

1 = Three-Dimensional mode enabled

DMA Interrupt Enable, Bit 22

DMA Address Mode, Bits 9–4

0 = Disables DMA Interrupt

Non-Three-Dimensional Addressing Modes (D3D=0)

1 = Enables DMA interrupt

DAM[2–0] = source

DAM[5–3] = Destination

DMA Transfer Mode, Bits 21–19

DAM[5–3]

Addressing Mode

Counter

Offset Register

DAM[2–0]

Mode

Selection

000

2D

B

DOR0

DTM[2:0]

Triggered By

DE Cleared

Transfer Mode

001

2D

B

DOR1

000

request

yes

block transfer

010

2D

B

DOR2

011

2D

B

DOR3

001

request

yes

word transfer

100

No update

A

None

010

request

yes

line transfer

101

Postincrement-by-1

A

None

011

DE

yes

block transfer

110–111

reserved

100

request

no

block transfer

Three-Dimensional Addressing Modes (D3D=1)

101

request

no

word transfer

110

reserved

DAM[5–3]

Addressing Mode

Offset Selection

000

2D

DOR0

111

reserved

001

2D

DOR1

010

2D

DOR2

011

2D

DOR3

DMA Channel Priority, Bits 18–17

100

No update

None

101

Postincrement-by-1

None

DPR[1:0]

Channel Priority

110

3D

DOR[0–1]

00

Priority level 0 (lowest)

111

3D

DOR[2–3]

01

Priority level 1

10

Priority level 2

DAM2

Addressing Mode

Offset Selection

0

Source: 3D

Source: DOR[0–1]

11

Priority level 3 (highest)

Destination: Defined by DAM[5–3]

1

Source: Defined by DAM[5–3]

DMA Continuous Mode Enable, Bit 16

Destination: 3D

Destination: DOR[2–3]

0 = Disables continuous mode

DAM

Counter

DCO Layout

1 = Enables continuous mode

[1–0]

00

Mode C

DCOH[23–12]

DCOM[11–6]

DCOL[5–0]

01

Mode D

DCOH[23–18]

DCOM[17–6]

DCOL[5–0]

DMA Request Source, Bits 15–11

10

Mode E

DCOH[23–18]

DCOM[17–12]

DCOL[11–0]

11

—

Reserved

DRS[4:0]

Requesting Device

00000–00011

External (IRQA,

IRQB,

IRQC,

IRQD)

DMA Destination Space, Bits 3–2

00100–01001

Transfer done from channel 0,1,2,3,4,5

DSS[1:0]

DMA Destination Memory

01010–01011

ESSI0 Receive, Transmit Data

00

X Memory Space

01100–01101

ESSI1 Receive, Transmit Data

01

Y Memory Space

10

P Memory Space

01110–01111

SCI Receive, Transmit Data

11

Reserved

10000–10010

Timer0, Timer1, Timer2

10011

Host Receive Data Full

DMA Source Space, Bits 1–0

10100

Host Transmit Data Empty

10101 - 11111

Reserved

DSS[1:0]

DMA Source Memory

00

X Memory Space

01

Y Memory Space

10

P Memory Space

11

Reserved

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

DE DIE

DTM[2–0]

DPR[1–0] DCON

DRS[4–0]

D3D

DAM[5–0]

DDS[1–0] DSS[1–0]

DMA Control Registers (DCR5–DCR0)	X:$FFFFD8, X:$FFFFDC, X:$FFFFE0,
Reset = $000000	X:$FFFFE4, X:$FFFFE8, X:$FFFFEC Read/Write

Figure B-9.DMA Control Registers 5–0 (DCR[5–0])

Programming Reference B-21