Index-2 DSP56301 User’s Manual

Bus Row Out-of-Page Wait States (BRW) bit 4-26Bus Software Triggered Reset (BSTR) bit 4-25Bus Strobe (BS) 2-7

Bus X Data Memory Enable (BXEN) bit 4-28Bus Y Data Memory Enable (BYEN) bit 4-28

Cache Burst Mode Enable (BE) bit 4-14Cache Enable (CE) bit 3-7,4-7,4-8Cache Line Size (CLS[7–0]) bits 6-69

Cache Line Size Configuraiton Register (CCLS) 6-34Carry (C) bit 4-11

Central Processing Unit (CPU) 1-1

Chip Operating Mode (MD–MA) bits 4-15Class Code/Revision ID Configuration Register

(CCCR/CRID) 6-67

PCI Device Base Class (BC[7–0]) 6-67

PCI Device Program Interface (P[17–10]) 6-67PCI Device Sub-Class (SC[7–0]) 6-67Revision ID (RID[7–0]) 6-67

Clear Transmitter (CLRT) bit 6-29clock 2-1,2-5

signals 2-5

Clock Divider (CD) bits 8-20clock generator 7-11,7-17Clock Generator (CLKGEN) 1-9Clock Out Divider (COD) 8-19Clock Output (CLKOUT) 2-5Clock Output Disable (COD) bit 4-21Clock Polarity (CKP) bit 7-22Clock Prescaler (SCP) 8-19

Clock Source Direction (SCKD) bit 7-22CMOS design 1-6

code compatibility 1-4codec 7-4,7-10,7-13

Column Address Strobe (CAS) 2-8COM byte 4-12

Condition Code Register (CCR) 4-7Carry (C) 4-11

Extension (E) 4-11Limit (L) 4-11Negative (N) 4-11Overflow (V) 4-11Scaling (S) 4-10Unnormalized (U) 4-11Zero (Z) 4-11

Control Register A (CRA) Alignment Control (ALC) 7-16Frame Rate Divider Control (DC) 7-16Prescale Modulus Select (PM) 7-16Prescaler Range (PSR) 7-16programming sheet B-32

Select SCK (SSC1) 7-15

Word Length Control (WL) 7-15Control Register B (CRB)

Clock Polarity (CKP) 7-22

Clock Source Direction (SCKD) 7-22Frame Sync Length (FSL) 7-22Frame Sync Polarity (FSP) 7-22Frame Sync Relative Timing (FSR) 7-22Mode Select (MOD) 7-21programming sheet B-33

Receive Enable (RE) 7-20

Receive Exception Interrupt Enable (REIE) 7-19Receive Interrupt Enable (RIE) 7-19

Receive Last Slot Interrupt Enable (RLIE) 7-19Serial Control Direction 0 (SCD0) 7-23Serial Control Direction 1 (SCD1) 7-23Serial Control Direction 2 (SCD2) 7-23Serial Output Flag 0 (OF0) 7-23

Serial Output Flag 1 (OF1) 7-23Shift Directions (SHFD) 7-22Synchronous/Asynchronous (SYN) 7-21Transmit 0 Enable (TE0) 7-20Transmit 1 Enable (TE1) 7-21Transmit 2 Enable (TE2) 7-21

Transmit Exception Interrupt Enable (TEIE) 7-19Transmit Interrupt Enable (TIE) 7-20Transmit Last Slot Interrupt Enable (TLIE) 7-19

control register mapping 5-2conventions,document 1-2core

Data ALU 1-4

Program Control Unit (PCU) 1-4Core Priority (CP) bits 4-7Core-DMA Priority (CDP) bits 4-14Crystal (XTAL) output 2-5

crystal frequency 8-6

Crystal Range (XTLR) bit 4-21

data alignment, input 6-3

Data Arithmetic Logic Unit (Data ALU) 1-4,1-6,1-7registers 1-7

data bus external 2-6signals 2-1,2-6

Data Input (DI) bit 9-29data memory expansion 1-5Data Output (DO) bit 9-29

Data Parity Reported (DPR) bit 6-65

Data Transfer Format Control (FC[1–0]) bits 6-31data transfer format converter 6-63

data transfer methods 5-2deadlock, HI32 6-46Debug Event (DE 2-29

Index-2

DSP56301 User’s Manual

DSP56301 specifications

The Motorola DSP56301 is a highly efficient digital signal processor, specifically engineered for real-time audio and speech processing applications. This DSP is part of Motorola's renowned DSP56300 family, which is recognized for its innovative features and outstanding performance in the realm of digital signal processing.

One of the main features of the DSP56301 is its ability to handle complex computations at high speeds. With a maximum clock frequency of 66 MHz, it delivers fast performance, enabling it to process audio signals in real time. The chip is built on a 24-bit architecture, which allows for high-resolution audio processing. This is particularly beneficial in applications such as telecommunications, consumer audio devices, and professional audio equipment, where precision is paramount.

The DSP56301 boasts a comprehensive instruction set that includes efficient mathematical operations, which are essential for digital filters and audio effects processing. One of the key innovations of this device is its dual data path architecture, which permits simultaneous processing of multiple data streams. This feature significantly enhances the device's throughput and responsiveness, making it suitable for demanding applications such as voice recognition and synthesis.

In terms of memory regions, the DSP56301 includes several on-chip memory categories, such as program memory, data memory, and a specialized memory for coefficients. The architecture's support for external memory expansion further increases its versatility, allowing designers to tailor systems to their specific requirements.

The DSP56301 implements advanced features such as a powerful on-chip hardware multiplier and accumulator, simplifying complex mathematical tasks and accelerating the execution of algorithms. Its flexible interrupt system enhances its capability to respond to time-sensitive operations, while the integrated serial ports facilitate efficient data communication with external devices.

Power consumption is also a vital characteristic of the DSP56301. It is designed with energy efficiency in mind, allowing for extended operation in battery-powered devices. The chip’s low power requirements are particularly advantageous in portable audio devices and other applications where energy conservation is crucial.

In conclusion, the Motorola DSP56301 is an exceptional digital signal processor that combines high processing power, flexibility, and efficiency. Its main features, advanced technologies, and robust architecture make it a top choice for developers seeking to create sophisticated audio and signal processing systems. With its enduring legacy in the industry, the DSP56301 continues to be relevant in a variety of modern applications, ensuring it remains a valuable tool for engineers and designers.

Motorola user manual Index-2 DSP56301 User’s Manual

Models: DSP56301

Index-2

DSP56301 User’s Manual

DSP56301 specifications