System Error Enable, Parity Error Response

Host-Side Programming Model

Table 6-26.Status/Command Configuration Register (CSTR/CCMR) Bit Definitions

Bit Number	Bit Name	Reset Value		Description


23	FBBC	0	Fast Back-to-Back Capable (hardwired to one)
			Indicates that the HI32 supports fast back-to-back transactions as a
			target in PCI mode (DCTR[HM] = $1). This bit is hardwired to one.

22–10		0	Reserved. Write to zero for future compatibility.

9		0	Not implemented. Write to zero for future compatibility.

8	SERE	0	System Error Enable
			Enable/disables HI32	HSERR	pin driving in PCI mode (DCTR[HM] =
			$1). When SERE is cleared, the HSERR pin is disabled (that is, high
			impedance). When SERE is set, the force system error bit
			DPCR[SERF] is set and the HI32 is an active PCI agent, or an address
			parity error is detected, which causes the HI32 to pulse the			HSERR	pin
			and set the signalled system error bit CSTR[SSE]. The personal
			hardware reset clears SERE.

7	WCC	0	Wait Cycle Control (hardwired to zero)

6	PERR	0	Parity Error Response
			Controls HI32 response to parity errors in PCI mode (DCTR[HM] = $1).
			When PERR is cleared, the HI32 does not drive HPERR. If PERR is set
			and a parity error is detected, the HI32 pulses the HPERR pin. If a
			parity error or HPERR low is detected, the HI32 sets the DPR bit in the
			CSTR/CCMR. In both cases, the HI32 sets bit 15 (DPE) in the
			CSTR/CCMR, sets DPER in the DPSR, and generates a parity error
			interrupt request if DPCR[PEIE] is set. The personal hardware reset
			clears PERE.

5–3		0	Not implemented. Write to zero for future compatibility.

2	BM	0	Bus Master Enable
			Controls HI32 ability to act as a master on the PCI bus in PCI mode
			(DCTR[HM] = $1). When BM is cleared, the HI32 is disabled from acting
			as a bus master; when BM is set, the HI32 can function as a bus
			master. This bit affects the MARQ bit in the DSP-side Status Register
			(DPSR). When BM is cleared, MARQ is also cleared. The personal
			hardware reset clears BM.

1	MSE	0	Memory Space Enable
			Controls the HI32 response to the PCI memory space accesses in PCI
			mode (DCTR[HM] = $1). The HI32 memory space response is disabled
			if MSE is cleared and enabled if MSE is set. The personal hardware
			reset clears MSE.

0		0	Not implemented. Write to zero for future compatibility.

6-66	DSP56301 User’s Manual

DSP56301 specifications

The Motorola DSP56301 is a highly efficient digital signal processor, specifically engineered for real-time audio and speech processing applications. This DSP is part of Motorola's renowned DSP56300 family, which is recognized for its innovative features and outstanding performance in the realm of digital signal processing.

One of the main features of the DSP56301 is its ability to handle complex computations at high speeds. With a maximum clock frequency of 66 MHz, it delivers fast performance, enabling it to process audio signals in real time. The chip is built on a 24-bit architecture, which allows for high-resolution audio processing. This is particularly beneficial in applications such as telecommunications, consumer audio devices, and professional audio equipment, where precision is paramount.

The DSP56301 boasts a comprehensive instruction set that includes efficient mathematical operations, which are essential for digital filters and audio effects processing. One of the key innovations of this device is its dual data path architecture, which permits simultaneous processing of multiple data streams. This feature significantly enhances the device's throughput and responsiveness, making it suitable for demanding applications such as voice recognition and synthesis.

In terms of memory regions, the DSP56301 includes several on-chip memory categories, such as program memory, data memory, and a specialized memory for coefficients. The architecture's support for external memory expansion further increases its versatility, allowing designers to tailor systems to their specific requirements.

The DSP56301 implements advanced features such as a powerful on-chip hardware multiplier and accumulator, simplifying complex mathematical tasks and accelerating the execution of algorithms. Its flexible interrupt system enhances its capability to respond to time-sensitive operations, while the integrated serial ports facilitate efficient data communication with external devices.

Power consumption is also a vital characteristic of the DSP56301. It is designed with energy efficiency in mind, allowing for extended operation in battery-powered devices. The chip’s low power requirements are particularly advantageous in portable audio devices and other applications where energy conservation is crucial.

In conclusion, the Motorola DSP56301 is an exceptional digital signal processor that combines high processing power, flexibility, and efficiency. Its main features, advanced technologies, and robust architecture make it a top choice for developers seeking to create sophisticated audio and signal processing systems. With its enduring legacy in the industry, the DSP56301 continues to be relevant in a variety of modern applications, ensuring it remains a valuable tool for engineers and designers.

Motorola DSP56301 System Error Enable, Wait Cycle Control hardwired to zero, Bus Master Enable

Models: DSP56301

Host-Side Programming Model

Fast Back-to-Back Capable (hardwired to one)

System Error Enable

impedance). When SERE is set, the force system error bit

Wait Cycle Control (hardwired to zero)

Parity Error Response

Bus Master Enable

Memory Space Enable

DSP56301 specifications