IL5 IL4, IL1 IL0, Maxlat, Mingnt | Motorola DSP56301 instruction

Host-Side Programming Model

6.8.13Interrupt Line-Interrupt Pin Configuration Register(CILP)

ML7 ML6

ML5 ML4 ML3 ML2 ML1 ML0

MG7 MG6 MG5 MG4 MG3 MG2

MG1 MG0

IP7

IP6

IP5

IP4

IP3

IP2

IP1

IP0

7	6	5	4	3	2	1	0

IL7	IL6	IL5	IL4	IL3	IL2	IL1	IL0

Hardwired to zero

Hardwired to one

Figure 6-22.Interrupt Line-Interrupt Pin Configuration Register(CILP)

CILP is PCI-standard read-only register mapped into the PCI configuration space in PCI mode or in mode 0 (HM = $1 or $0). CILP is accessed when a configuration read command is in progress and the PCI address is $FC. The DSP56300 core cannot access CILP. The host can access CILP only in PCI mode (HM≠$1). The 24 most significant bits of the CILP register are hardwired and are unaffected by any type of reset.

Table 6-30.Interrupt Line-Interrupt Pin Configuration Register(CILP) Bit Definitions

Bit Number	Bit Name	Reset Value	Description


31–24	ML[7–0]	0 (Hardwired)	MAX_LAT
			Specifies how often the device needs to gain access to the PCI bus.
			Because the HI32 has no major requirements for the settings of Latency
			Timers, these bits are hardwired to zero.

23–16	MG[7–0]	0 (Hardwired)	MIN_GNT
			Specifies how long a burst the device needs. Because the HI32 has no
			major requirements for the settings of Latency Timers, these bits are
			hardwired to zero.

15–8	IP[7–0]	1 (Hardwired)	Interrupt Pin
			Specifies which interrupt the device uses. A value of 1 corresponds to
			PCI INTA.

7–0	IL[7–0]	0	Interrupt Line
			Communicates PCI interrupt line routing information. POST software
			writes the routing information into these bits as it initializes and
			configures the PCI system.

Host Interface (HI32)

6-73

DSP56301 specifications

The Motorola DSP56301 is a highly efficient digital signal processor, specifically engineered for real-time audio and speech processing applications. This DSP is part of Motorola's renowned DSP56300 family, which is recognized for its innovative features and outstanding performance in the realm of digital signal processing.

One of the main features of the DSP56301 is its ability to handle complex computations at high speeds. With a maximum clock frequency of 66 MHz, it delivers fast performance, enabling it to process audio signals in real time. The chip is built on a 24-bit architecture, which allows for high-resolution audio processing. This is particularly beneficial in applications such as telecommunications, consumer audio devices, and professional audio equipment, where precision is paramount.

The DSP56301 boasts a comprehensive instruction set that includes efficient mathematical operations, which are essential for digital filters and audio effects processing. One of the key innovations of this device is its dual data path architecture, which permits simultaneous processing of multiple data streams. This feature significantly enhances the device's throughput and responsiveness, making it suitable for demanding applications such as voice recognition and synthesis.

In terms of memory regions, the DSP56301 includes several on-chip memory categories, such as program memory, data memory, and a specialized memory for coefficients. The architecture's support for external memory expansion further increases its versatility, allowing designers to tailor systems to their specific requirements.

The DSP56301 implements advanced features such as a powerful on-chip hardware multiplier and accumulator, simplifying complex mathematical tasks and accelerating the execution of algorithms. Its flexible interrupt system enhances its capability to respond to time-sensitive operations, while the integrated serial ports facilitate efficient data communication with external devices.

Power consumption is also a vital characteristic of the DSP56301. It is designed with energy efficiency in mind, allowing for extended operation in battery-powered devices. The chip’s low power requirements are particularly advantageous in portable audio devices and other applications where energy conservation is crucial.

In conclusion, the Motorola DSP56301 is an exceptional digital signal processor that combines high processing power, flexibility, and efficiency. Its main features, advanced technologies, and robust architecture make it a top choice for developers seeking to create sophisticated audio and signal processing systems. With its enduring legacy in the industry, the DSP56301 continues to be relevant in a variety of modern applications, ensuring it remains a valuable tool for engineers and designers.

Motorola DSP56301 Interrupt Line-Interrupt Pin Configuration RegisterCILP, IL5 IL4, IL1 IL0

Models: DSP56301

Host-Side Programming Model

6.8.13Interrupt Line-Interrupt Pin Configuration Register(CILP)

IL5

IL4

IL1

IL0

Figure 6-22.Interrupt Line-Interrupt Pin Configuration Register(CILP)

MAX_LAT

MIN_GNT

Interrupt Line

Host Interface (HI32)

DSP56301 specifications