;

HA[10]

<-

SBHE_

; selects HI32 (base address 10011111)

;

HA[9]

<-

SA[0]

; selects HI32 (base address 10011111)

;

HA[8:3]

<-

SA[9:4]

; selects HI32 (base address 10011111)

;

HA[2:0] <-

SA[3:1]

; selects HTXR registers

;

HD[15:0] - SD[15:0]

; Data bus

;

HD[23:16] - Not connected

; High Data Bus - Should be pulled up or down

;

HDBEN_

-> OE_

; Output enable of transcievers

;

HDBDR

-> DIR

; Direction of transcievers

;

HSAK_

-> IO16_

; 16 bit data word

;

HBS_

<- Vcc

; Bus Strobe disabled

;

HAEN

<- AEN

; DMA cycle enable

;

HTA

-> CHRDY

; Channel ready

;

HWR_

<- IOWC_

; IO/DMA write strobe

;

HRD_

<- IORC_

; IO/DMA read strobe

;

HRST

<- inverted RSTDRV

; invert ISA reset

;

 

 

 

 

;

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

;

If MD:MC:MB:MA=x110,

then it loads the program

RAM

from

the Host

;

Interface programmed

to operate in the Universal

Bus

(UB)

mode, in

;double-strobe pin configuration.

; The HI32 bootstrap

code expects

first

to receive

3 bytes specifying

the

; number

of program

words,

then

3 bytes specifying the address to

 

; start

loading

the program

words

and then 3 bytes for each program

word

; to be loaded.

The number of words,

the starting

address

and the program

; words

are received

least significant

byte first

followed

by the mid and

;then by the most significant byte.

; The program words will

be condensed

into 24-bit words and stored in

; contiguous

PRAM

memory

locations starting at the specified starting

; address.

After

reading

the program

words, program execution starts

;from the same address where loading started.

;

The Host Interface

bootstrap

load program may be stopped by setting

the

;

Host Flag 0 (HF0)

in HCTR

register. This will start execution of

the

;loaded program from the specified starting address.

;The user must externally decode the port address with active low logic and

;connect the select line to HAEN; all the address lines shall be pulled down

;except for HA3, HA2 and HA1 that select the HOST Interface registers.

;

;When booting through the Host Interface it is recommended that the Host

;boot program verify that the Host Interface is operational by

;reading the status register (HSTR) and confirm that TRDY=1.

;

 

 

 

 

 

 

 

; When

booting through

the

Host Interface,

it is recommended

that the

; HOST

Processor’s

boot

program verify

that the Host Interface

is

; ready

by reading

the status

register

(HSTR)

and confirm that

TRDY=1

;or HTRQ=1.

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

;

If MD:MC:MB:MA=x111,

then it loads the program

RAM

from

the Host

;

Interface programmed

to operate in the Universal

Bus

(UB)

mode, in

;single-strobe pin configuration.

;Other than the single-strobe pin configuration, this mode is identical to

;the double-strobe pin configuration UB mode (MD:MC:MB:MA=x110).

DSP56301 User’s Manual

A-5

Page 301
Image 301
Motorola DSP56301 user manual Hdben

DSP56301 specifications

The Motorola DSP56301 is a highly efficient digital signal processor, specifically engineered for real-time audio and speech processing applications. This DSP is part of Motorola's renowned DSP56300 family, which is recognized for its innovative features and outstanding performance in the realm of digital signal processing.

One of the main features of the DSP56301 is its ability to handle complex computations at high speeds. With a maximum clock frequency of 66 MHz, it delivers fast performance, enabling it to process audio signals in real time. The chip is built on a 24-bit architecture, which allows for high-resolution audio processing. This is particularly beneficial in applications such as telecommunications, consumer audio devices, and professional audio equipment, where precision is paramount.

The DSP56301 boasts a comprehensive instruction set that includes efficient mathematical operations, which are essential for digital filters and audio effects processing. One of the key innovations of this device is its dual data path architecture, which permits simultaneous processing of multiple data streams. This feature significantly enhances the device's throughput and responsiveness, making it suitable for demanding applications such as voice recognition and synthesis.

In terms of memory regions, the DSP56301 includes several on-chip memory categories, such as program memory, data memory, and a specialized memory for coefficients. The architecture's support for external memory expansion further increases its versatility, allowing designers to tailor systems to their specific requirements.

The DSP56301 implements advanced features such as a powerful on-chip hardware multiplier and accumulator, simplifying complex mathematical tasks and accelerating the execution of algorithms. Its flexible interrupt system enhances its capability to respond to time-sensitive operations, while the integrated serial ports facilitate efficient data communication with external devices.

Power consumption is also a vital characteristic of the DSP56301. It is designed with energy efficiency in mind, allowing for extended operation in battery-powered devices. The chip’s low power requirements are particularly advantageous in portable audio devices and other applications where energy conservation is crucial.

In conclusion, the Motorola DSP56301 is an exceptional digital signal processor that combines high processing power, flexibility, and efficiency. Its main features, advanced technologies, and robust architecture make it a top choice for developers seeking to create sophisticated audio and signal processing systems. With its enduring legacy in the industry, the DSP56301 continues to be relevant in a variety of modern applications, ensuring it remains a valuable tool for engineers and designers.