Motorola DSP56301 user manual Pll, Clock Signals, Phase-Lock Loop Signals

Clock

2.3Clock

			Table 2-4.Clock Signals
Signal	Type	State During		Signal Description
Name		Reset
EXTAL	Input	Input		External Clock/Crystal Input—Interfaces the internal crystal oscillator
				input to an external crystal or an external clock.
XTAL	Output	Chip-driven		Crystal Output—Connects the internal crystal oscillator output to an
				external crystal. If an external clock is used, leave XTAL unconnected.

2.4PLL

Table 2-5.Phase-Lock Loop Signals

Signal Name	Type	State During	Signal Description
		Reset
PCAP	Input	Input	PLL Capacitor—Connects an off-chip capacitor to the PLL filter.
			Connect one capacitor terminal to PCAP and the other terminal to
			VCCP.
			If the PLL is not used, PCAP may be tied to VCC, GND, or left
			floating.
CLKOUT	Output	Chip-driven	Clock Output—An output clock synchronized to the internal core
			clock phase.
			Note: If the PLL is enabled and both the multiplication and division
			factors equal one, then CLKOUT is also synchronized to EXTAL. If
			the PLL is disabled, the CLKOUT frequency is half the frequency of
			EXTAL.
			PLL Initial—During assertion of		, the value of PINIT is
PINIT	Input	Input		RESET
			written into the PLL enable (PEN) bit of the PLL control (PCTL)
			register, determining whether the PLL is enabled or disabled.

Signals/Connections 2-5