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Motorola DSP56301 user manual Data Transfer Paths, Host-to-DSP Data Path

Models: DSP56301

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Data Transfer Paths

DMA controllers, or standard peripheral buses (for example, ISA/EISA) because the interface appears to the host as static RAM.

A host command feature enables the host processor to issue vectored interrupt requests to the DSP56300 core. Writing to a vector address register in the HI32, the host can select any one of 128 DSP56300 core interrupt routines to execute. This flexibility allows the host programmer to execute up to 128 pre-programmed functions inside the DSP. For example, host exceptions can allow the host processor to read or write DSP registers, X, Y, or program memory locations, force exception handlers (for example, SSI, Timer, IRQA, IRQB exception routines), and perform control and debugging operations if exception routines are implemented in the DSP to perform these tasks. The host processor can also generate non-maskable interrupt requests to the DSP56300 core using the host commands.

6.3Data Transfer Paths

The master data transfer format control bits (FC[1–0] in the DPMC) affect the HTXR-DRXR and DTXM-HRXM data paths only (see Table 6-3,HI32 (PCI Master Data Transfer Formats, on page 6-8). The target data transfer format control bits (HTF[1–0] and HRF[1–0] in the HCTR) affect the HTXR–DRXR and DTXS–HRXS data paths only (see Table 6-4,Transmit Data Transfer Format, on page 6-9and Table 6-5,Receive Transfer Data Formats, on page 6-10). The data paths to the other host registers are not affected by the data transfer format control bits.

6.3.1Host-to-DSP Data Path

In PCI mode data transfers in which the HI32 is the master (DCTR[HM] = $1) with DPMC[FC]≠$0, the host-to-DSP data path is a 24-bit wide FIFO that is six words deep. The host data is written into the host side of the FIFO (HTXR) as 24-bit words, and the DSP56300 core reads 24-bit words from the DSP side (DRXR). In PCI mode data transfers in which the HI32 is the master (DCTR[HM] = $1) with DPMC[FC] = $0, and In PCI mode data transfers in which the HI32 is the target (DCTR[HM] = $1) with HTF = $0, the host-to-DSP data path operates 32-bit wide FIFO that is three words deep. The host data is written into the HTXR as 32-bit words, and the DSP56300 core reads 24-bit words from the DRXR. Each word read by the DSP56300 core contains 16 bits of data, right aligned and zero extended. The first word read by the DSP56300 core contains the two least significant bytes of the 32-bit word read into the HTXR. The second word contains the two most significant bytes of the 32-bit word read into the HTXR. As the active target, in a memory space write transaction, the HTXR is accessed if the PCI address is between HI32_base_address: $01C and HI32_base_address: $FFFC (that is, the host process or views HTXR as a 16377 Dword write-only memory). As the active master, all data read from the target is written to the HTXR.

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DSP56301 User’s Manual

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Motorola DSP56301 user manual Data Transfer Paths, Host-to-DSP Data Path
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DSP56301 specifications

The Motorola DSP56301 is a highly efficient digital signal processor, specifically engineered for real-time audio and speech processing applications. This DSP is part of Motorola's renowned DSP56300 family, which is recognized for its innovative features and outstanding performance in the realm of digital signal processing.

One of the main features of the DSP56301 is its ability to handle complex computations at high speeds. With a maximum clock frequency of 66 MHz, it delivers fast performance, enabling it to process audio signals in real time. The chip is built on a 24-bit architecture, which allows for high-resolution audio processing. This is particularly beneficial in applications such as telecommunications, consumer audio devices, and professional audio equipment, where precision is paramount.

The DSP56301 boasts a comprehensive instruction set that includes efficient mathematical operations, which are essential for digital filters and audio effects processing. One of the key innovations of this device is its dual data path architecture, which permits simultaneous processing of multiple data streams. This feature significantly enhances the device's throughput and responsiveness, making it suitable for demanding applications such as voice recognition and synthesis.

In terms of memory regions, the DSP56301 includes several on-chip memory categories, such as program memory, data memory, and a specialized memory for coefficients. The architecture's support for external memory expansion further increases its versatility, allowing designers to tailor systems to their specific requirements.

The DSP56301 implements advanced features such as a powerful on-chip hardware multiplier and accumulator, simplifying complex mathematical tasks and accelerating the execution of algorithms. Its flexible interrupt system enhances its capability to respond to time-sensitive operations, while the integrated serial ports facilitate efficient data communication with external devices.

Power consumption is also a vital characteristic of the DSP56301. It is designed with energy efficiency in mind, allowing for extended operation in battery-powered devices. The chip’s low power requirements are particularly advantageous in portable audio devices and other applications where energy conservation is crucial.

In conclusion, the Motorola DSP56301 is an exceptional digital signal processor that combines high processing power, flexibility, and efficiency. Its main features, advanced technologies, and robust architecture make it a top choice for developers seeking to create sophisticated audio and signal processing systems. With its enduring legacy in the industry, the DSP56301 continues to be relevant in a variety of modern applications, ensuring it remains a valuable tool for engineers and designers.