Motorola DSP56301 Bus Address to Compare, Bits, Bus Number of Address Bits to Compare, Bits

Models: DSP56301

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Programming Sheets

Application:

 

 

Date:

 

 

 

 

 

 

 

 

Programmer:

 

Sheet 3 of 3

Bus Interface Unit

Bus Address to Compare, Bits 23–12

BAC[11–0] = address to compare to the external address in order to decide whether to assert the AA pin

Bus Number of Address Bits to Compare, Bits 11–8

BNC[3–0] = number of bits (from BAC bits) that are compared to the external address

(Combinations BNC[3–0] = 1111, 1110, 1101 are reserved.)

Bus Packing Enable, Bit 7

0 = Disable internal packing/unpacking logic

1 = Enable internal packing/unpacking logic

Bus Y Data Memory Enable, Bit 5

0 = Disable AA pin and logic during external Y data space accesses

1 = Enable AA pin and logic during external Y data space accesses

Bus X Data Memory Enable, Bit 4

0 = Disable AA pin and logic during external X data space accesses

1 = Enable AA pin and logic during external X data space accesses

Bus Program Memory Enable, Bit 3

0 = Disable AA pin and logic during external program space accesses

1 = Enable AA pin and logic during external program space accesses

Bus Address Attribute Polarity, Bit 2

0 = AA/RAS signal is active low

1 = AA/RAS signal is active high

Bus Access Type, Bits 1–0

BAT[1–0]

Encoding

00

Reserved

 

 

01

SRAM access

10DRAM access

11Reserved

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

 

6

5

4

3

2

1

0

 

 

BAC11

BAC10

BAC9

BAC8

BAC7

BAC6

BAC5

BAC4

BAC3

BAC2

BAC1

BAC0

BNC3

BNC2

BNC1

BNC0

BAC7

 

*0

 

BYEN

BXEN

BPEN

BAAP

BAT1

BAT0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Address Attribute Registers 3 (AAR3)

 

X:$FFFFF6 Read/Write

 

 

 

 

 

 

 

 

 

 

Address Attribute Registers 2 (AAR2)

 

X:$FFFFF7 Read/Write

 

 

 

 

 

 

 

 

 

 

Address Attribute Registers 1

(AAR1)

 

X:$FFFFF8 Read/Write

 

 

 

 

 

 

 

 

 

 

Address Attribute Registers 0

(AAR0)

 

X:$FFFFF9 Read/Write

 

 

 

 

 

 

 

 

 

 

Reset = $000000

 

 

 

 

 

 

 

 

 

 

 

 

 

 

* = Reserved, Program as 0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Figure B-8.Address Attribute Registers (AAR[3–0])

B-20

DSP56301 User’s Manual

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Motorola DSP56301 Bus Address to Compare, Bits, Bus Number of Address Bits to Compare, Bits, Bus Packing Enable, Bit

DSP56301 specifications

The Motorola DSP56301 is a highly efficient digital signal processor, specifically engineered for real-time audio and speech processing applications. This DSP is part of Motorola's renowned DSP56300 family, which is recognized for its innovative features and outstanding performance in the realm of digital signal processing.

One of the main features of the DSP56301 is its ability to handle complex computations at high speeds. With a maximum clock frequency of 66 MHz, it delivers fast performance, enabling it to process audio signals in real time. The chip is built on a 24-bit architecture, which allows for high-resolution audio processing. This is particularly beneficial in applications such as telecommunications, consumer audio devices, and professional audio equipment, where precision is paramount.

The DSP56301 boasts a comprehensive instruction set that includes efficient mathematical operations, which are essential for digital filters and audio effects processing. One of the key innovations of this device is its dual data path architecture, which permits simultaneous processing of multiple data streams. This feature significantly enhances the device's throughput and responsiveness, making it suitable for demanding applications such as voice recognition and synthesis.

In terms of memory regions, the DSP56301 includes several on-chip memory categories, such as program memory, data memory, and a specialized memory for coefficients. The architecture's support for external memory expansion further increases its versatility, allowing designers to tailor systems to their specific requirements.

The DSP56301 implements advanced features such as a powerful on-chip hardware multiplier and accumulator, simplifying complex mathematical tasks and accelerating the execution of algorithms. Its flexible interrupt system enhances its capability to respond to time-sensitive operations, while the integrated serial ports facilitate efficient data communication with external devices.

Power consumption is also a vital characteristic of the DSP56301. It is designed with energy efficiency in mind, allowing for extended operation in battery-powered devices. The chip’s low power requirements are particularly advantageous in portable audio devices and other applications where energy conservation is crucial.

In conclusion, the Motorola DSP56301 is an exceptional digital signal processor that combines high processing power, flexibility, and efficiency. Its main features, advanced technologies, and robust architecture make it a top choice for developers seeking to create sophisticated audio and signal processing systems. With its enduring legacy in the industry, the DSP56301 continues to be relevant in a variety of modern applications, ensuring it remains a valuable tool for engineers and designers.