Manuals / Motorola / Home Audio / Stereo System

Motorola DSP56301 user manual Rep Mac x0,x1,a x,lr0+

Models: DSP56301

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Page 309

rep	n0
mac x0,x1,a x,l:(r0)+		;; exercise mac, write x/y ram
else		;; x/y ram not symmetrical
;; write x memory
clr a	#start_xram,r0	;; start of xram
move	#>length_xram,n0	;; length of xram
rep	n0
mac x0,y0,a x1,x:(r0)+		;; exercise mac, write xram
;; write y memory
clr a	#start_yram,r1	;; start of yram
move	#>length_yram,n1	;; length of yram
rep	n1
mac x1,y0,a x0,y:(r1)+		;; exercise mac, write yram
endif
;; write p memory
clr a	#start_pram,r2	;; start of pram
move	#>length_pram,n2	;; length of pram
rep	n2
move	y0,p:(r2)+	;; write pram

	;; check memory contents
if	(EQUALDATA)		;; x/y ram symmetrical
	;; check dram
	clr a	#start_dram,r0	;; restore pointer, clear a
	do	n0,_loopd
	move	x:(r0),a1	;; a0=a2=0
	eor	x1,a
	add	a,b	;; accumulate error in b
	move	y:(r0)+,a1	;; a0=a2=0
	eor	x0,a
	add	a,b	;; accumulate error in b
_loopd
else			;; x/y ram not symmetrical
	;; check xram
	clr a	#start_xram,r0	;; restore pointer, clear a
	do	n0,_loopx
	move	x:(r0)+,a1	;; a0=a2=0
	eor	x1,a
	add	a,b	;; accumulate error in b
_loopx
	;; check yram
	clr a	#start_yram,r1	;; restore pointer, clear a
	do	n1,_loopy
	move	y:(r1)+,a1	;; a0=a2=0
	eor	x0,a
	add	a,b	;; accumulate error in b
_loopy

endif

DSP56301 User’s Manual

A-13

Page 309

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Motorola DSP56301 user manual Rep Mac x0,x1,a x,lr0+

DSP56301 specifications

The Motorola DSP56301 is a highly efficient digital signal processor, specifically engineered for real-time audio and speech processing applications. This DSP is part of Motorola's renowned DSP56300 family, which is recognized for its innovative features and outstanding performance in the realm of digital signal processing.

One of the main features of the DSP56301 is its ability to handle complex computations at high speeds. With a maximum clock frequency of 66 MHz, it delivers fast performance, enabling it to process audio signals in real time. The chip is built on a 24-bit architecture, which allows for high-resolution audio processing. This is particularly beneficial in applications such as telecommunications, consumer audio devices, and professional audio equipment, where precision is paramount.

The DSP56301 boasts a comprehensive instruction set that includes efficient mathematical operations, which are essential for digital filters and audio effects processing. One of the key innovations of this device is its dual data path architecture, which permits simultaneous processing of multiple data streams. This feature significantly enhances the device's throughput and responsiveness, making it suitable for demanding applications such as voice recognition and synthesis.

In terms of memory regions, the DSP56301 includes several on-chip memory categories, such as program memory, data memory, and a specialized memory for coefficients. The architecture's support for external memory expansion further increases its versatility, allowing designers to tailor systems to their specific requirements.

The DSP56301 implements advanced features such as a powerful on-chip hardware multiplier and accumulator, simplifying complex mathematical tasks and accelerating the execution of algorithms. Its flexible interrupt system enhances its capability to respond to time-sensitive operations, while the integrated serial ports facilitate efficient data communication with external devices.

Power consumption is also a vital characteristic of the DSP56301. It is designed with energy efficiency in mind, allowing for extended operation in battery-powered devices. The chip’s low power requirements are particularly advantageous in portable audio devices and other applications where energy conservation is crucial.

In conclusion, the Motorola DSP56301 is an exceptional digital signal processor that combines high processing power, flexibility, and efficiency. Its main features, advanced technologies, and robust architecture make it a top choice for developers seeking to create sophisticated audio and signal processing systems. With its enduring legacy in the industry, the DSP56301 continues to be relevant in a variety of modern applications, ensuring it remains a valuable tool for engineers and designers.

Contents

Revision 3, March DSP56301 User’s ManualUSA/EUROPE How to reach usJapan ASIA/PACIFICPage Page Contents Chapter Core Configuration Chapter Memory ConfigurationChapter Host Interface HI32 Chapter Programming the PeripheralsChapter Enhanced Synchronous Serial Interface Essi Chapter Serial Communication Interface SCI Chapter Triple Timer Module Chapter a Bootstrap Program Chapter B Programming ReferenceIndex DSP56301 User’s Manual FiguresXii Pulse Width Modulation Toggle Mode, TRM = DSP Control Register Dctr DSP PCI Control Register Dpcr Tables TablesEssi Clock Sources Overview Manual OrganizationSignal/Symbol Logic State Signal State Voltage High True/Low True Signal ConventionsManual Conventions Ground2PIN is a generic term for any pin on the chip GroundDSP56300 Core Features Program RAM Instruction Data RAM Switch Size Cache Size CE = MS =Size Cache Data ALU DSP56300 Core Functional BlocksAddress Generation Unit AGU Data ALU RegistersMultiplier-Accumulator MAC Program Control Unit PCU Jtag TAP and OnCE Module PLL and Clock OscillatorDSP56301 Switch Memory Configuration Internal BusesOn-Chip Memory DMA Memory Expansion AreaExpansion Area Peripherals General-Purpose Input/Output Gpio signalsHost Interface HI32 Enhance Synchronous Serial Interface EssiSerial Communications Interface SCI Triple Timer ModuleDSP56301 Documentation Related Documents and Web SitesName Description Order Number DSP56300FM/ADTimers JTAG/OnCE Port DSP56301 Functional Signal GroupingsEnhanced Synchronous Serial Interfaces ESSI0 ESSI1See -2for a listing of the Host Interface/Port B Signals DSP56301Port a Host Interface/Port B Detail Signal Diagram Power Inputs PowerGround Signals GroundPhase-Lock Loop Signals Clock SignalsClock PLLExternal Address Bus External Memory Expansion Port Port aExternal Data Bus External Bus ControlArbitration is reset to the bus slave state Signals are tri-statedOutput Tri-stated Is an active-low output that is Output Tri-stated Is asserted for half a clockBclk CASInterrupt and Mode Control Interrupt and Mode ControlSignal State Type During Signal Description Name Nonmaskable Interrupt-After10.Host Interface Host Interface HI32Command 0-3/Byte Enable 0-3 -When the HI32 is programmed Hpar HBSHdak HperrHirq HserrHstop HWRSignal PCI Mode Enhanced Universal Bus Mode Gpio Mode Name 11.Summary of HI32 Signals and ModesHAD10 HD2 HIO10 HP8 HAD8 HD0 HIO8 HP9 HAD9 HD1 HIO9HAD11 HD3 HIO11 HAD12 HD4 HIO1212.Host Port Pins HI32 PCIGpio Host Target Ready Host Data Bus Enable Bus Command/Byte Enable Host Address BusReserved Host Initiator Ready Host Data Bus DirectionBus Grant Host Address Enable Parity Error DMA RequestHost Device Select Host Select Acknowledge Host Lock Bus StrobeBus Request Host Transfer Acknowledge Host System Error Host Interrupt RequestHreq is deasserted in the same PCI HstrHost Stop Host Write/Read-Write Hstop HWR/HRWHRD/HDS Initialization Device Select Host Read/Data StrobeAddress/Data Multiplexed Bus Data Bus Host Bus ClockEnhanced Synchronous Serial Interface Hardware ResetHost Interrupt a Active low, open drain output pinPC0 13.Enhanced Synchronous Serial InterfacePC1 PC2PC3 SCK0SRD0 PC4PD0 14.Enhanced Serial Synchronous InterfacePD1 PD2PD3 SCK1SRD1 PD4Timers Serial Communications Interface SCI15.Serial Communication Interface Timer 0 Schmitt-Trigger Input/Output- When Timer 16.Triple Timer SignalsTimer 1 Schmitt-Trigger Input/Output- When Timer Timer 2 Schmitt-Trigger Input/Output- When timerSignal Name Type State During Signal Description Reset Jtag and OnCE Interface17.JTAG/OnCE Interface Jtag and OnCE Interface DSP56301 User’s Manual Program Memory Space Memory ConfigurationMemory Switch Modes-Program Memory Internal Program MemoryInstruction Cache Memory Switch Modes-X Data Memory Program Bootstrap ROMMemory Configuration Data Memory SpaceMemory Switch Modes-Y Data Memory Internal I/O Space-X Data MemoryInternal Y Data Memory External I/O Space-Y Data Memory Dynamic Memory Configuration SwitchingInternal Memory Configuration Summary Sixteen-Bit Compatibility Mode ConfigurationDSP56301 RAM Configurations DSP56301 RAM Address Ranges by ConfigurationDefault Memory MapsRAM None 64K $000-$FFF $000-$7FF 16-Bit Space With Default RAM 0, 0$000-$800 $000-$BFF 16MNone 64K $000-$7FF $000-$BFF 16-Bit Space With Switched Program RAM 0, 1$000-$BFF $000-$7FF Not addressable Instruction Cache Enabled 1, 016-Bit Space With Instruction Cache Enabled 1, 0 $000-$3FF $000-$BFF Not addressable Addressable$0400 $0000 Core Configuration Core ConfigurationOperating Modes Reset Description VectorDSP56301 Operating Modes ModeMode Description Operating Mode DefinitionsAddress attributes selected default Low. The DSP56301 is written with 24-bit-wide wordsDSP Clkout rate must be 5/3 of the PCI clock Bootstrap Program Status Register SR Central Processor Unit CPU RegistersDMA OMR Sixteen-Bit Arithmetic Mode Cache EnableDo Forever Flag Do Loop FlagSixteen-Bit Compatibility Mode Scaling Rounding Bit SEquation Mode Scaling ModeInterrupt Mask Priority Exceptions Exceptions Masked PermittedScaling Mode Integer Portion Bit Number Bit Name Reset Value Description LimitExtension UnnormalizedOperating Mode Register OMR Bit Definitions Operating Mode Register OMRStack Extension Enable Stack Extension Wrap FlagAddress Attribute Priority Disable Address Trace EnableAsynchronous Bus Arbitration Enable Stack Extension Overflow FlagMemory Switch Mode Cache Burst Mode EnableBus Release Timing Synchronize SelectBit Number Bit Name Reset Value Description Stop Delay Mode Configuring InterruptsExternal Bus Disable Chip Operating ModeInterrupt Priority Registers Iprc and Iprp Interrupt Table Memory Map Interrupt Priority Level BitsInterrupt Sources VBA$1C VBA$1AVBA$1E VBA$2AProcessing Interrupt Source Priorities Within an IPL Interrupt Source Priorities Within an IPLPriority Interrupt Source TIMER0 overflow interrupt Host command interruptTIMER0 compare interrupt TIMER1 overflow interruptPLL Control Register Pctl Bit Definitions PLL Control Register PctlBus Control Register Bus Interface Unit BIU RegistersBus Area 3 Wait State Control Bus Default Area Wait State ControlBus Area 2 Wait State Control Bus Area 1 Wait State ControlBRP BRF7 BRF6 Dram Control Register DCRBRF3 BRF2 BRF1 Bstr Bren BME Bple BPS110.DRAM Control Register DCR Bit Definitions Bus Dram Page Size Bus Page Logic EnableBus Row Out-of-page Wait States Bus Column In-Page Wait StateAddress Attribute Registers AAR0-3 Bus Address to CompareBus Number of Address Bits to Compare Bus Y Data Memory Enable Bus Packing EnableBus X Data Memory Enable Bus Program Memory EnableDIE DTM2 DTM1 DTM0 DMA Control Registers 5-0 DCR5-0Dcon DAM5 DAM4 DAM3 DAM2 DAM1 DAM0DMA Transfer Mode DMA Interrupt EnableDTM2-0 Trigger Cleared Transfer Mode After 12.DMA Control Register DCR Bit DefinitionsDMA Channel Priority Number ValueDMA address generation logic, buses, and so forth DPR1-0 Channel PriorityDMA Continuous Mode Enable OMR CDP1-0 CP1-0 Core PriorityDcon Three-Dimensional Mode DMA Request SourceDRS4-0 Requesting Device Device Identification Register IDR DDS1 DDS0DSS1 DSS0 Jtag Boundary Scan Register BSR Jtag Identification ID RegisterVersion Information Design Center Number Identity See NoteJtag Boundary Scan Register BSR DSP56301 User’s Manual Programming the Peripherals Peripheral Initialization StepsData Transfer Methods Mapping the Control RegistersPolling Data MemoryInterrupts General-Purpose Input/Output Gpio 3 DMAAdvantages and Disadvantages Port B Signals and Registers Port C Signals and Registers Port D Signals and RegistersPort E Signals and Registers Timer Gpio Triple Timer Signals and RegistersGeneral-Purpose Input/Output Gpio DSP56301 User’s Manual Host Interface HI32 FeaturesHI32 Features, Core-Side and Host-Side HI32 Features in PCI Mode and Universal Bus Mode Overview DSP-Side Registers PCI Configuration SpaceDSP DMA Data Bus DSP Global Data Bus Data transfer format converterHost-to-DSP Data Path Data Transfer PathsDSP-To-Host Data Path Dpmc HI32 PCI Master Data Transfer FormatsFC1 FC0 Two least significant bytes of two HrxmTransmit Data Transfer Format HctrHTF1 HTF0 DSP to Host Data Transfer Format Receive Transfer Data FormatsHRF Three least significant Hrxs bytesReceive Transfer Data Formats Type Entered when Description Reset StatesDSP-Side Operating Modes HRST/HRSTPCI Mode Dctrhm = $1 Terminate and Reset Dctrhm = $0HI32 Mode PCIExample 6-1. PCI /DMA Throughput 32-Bit Multfactor Self-Configuration Mode Dctrhm = $5 Gpio Mode Dctrhm = $4Example 6-3. Self-Configuration Procedure for PCI Mode Host Port Pins PCI Bus Universal Bus ModeHost Port Pin Functionality DSP56301 ISA Slave MasterMemory Register Address Mode HI32 DSP-Side Programming ModelHI32 Programming Model, DSP Side Mode Description Value DSP Control Register DctrBit Number Bit Name 10.DSP Control Register Dctr Bit Definitions Htap Host Data Strobe ModeHost Transfer Acknowledge Polarity Host Read/Write PolaritySlave Transmit Interrupt Enable Slave Receive Interrupt EnableHost Command Interrupt Enable DSP PCI Control Register DpcrReceive Buffer Lock Enable Insert Address Enable11.DSP PCI Control Register Dpcr Bit Definitions IAEMaster Access Counter Enable Master Wait State DisableForce HserrTransaction Termination Interrupt Enable Transfer Complete Interrupt EnableTransaction Abort Interrupt Enable Parity Error Interrupt EnableDSP PCI Master Control Register Dpmc BL4BL1 BL0 Data Transfer Format Control 12.DSP PCI Master Control Register Dmpc Bit DefinitionsA PCI DSP-to-Host transaction A PCI Host-to-DSP transactionDSP PCI Transaction Address High PCI Data Burst Length13.DSP PCI Address Register Dpar Bit Definitions DSP PCI Address Register DparBE2 BE1 AR9 AR8 AR7 AR6 AR5 AR4 AR3 AR2 AR1 AR0C3-0 Command Type PCI Bus CommandDSP PCI Transaction Address Low AR1 AR0DSP Status Register DSR Bit Bit Name Reset Mode Description Number Value14.DSP Status Register DSR Bit Definitions 2322212019181716Slave Receive Data Request Srrq UBMHost Command Pending Mode Description Number Value14. DSP Status Register DSR Bit Definitions Slave Transmit Data Request15.DSP PCI Status Register Dpsr Bit Definitions DSP PCI Status Register DpsrRdcq MDT Hdtc Trty Tdis TAB MAB Aper Marq Mrrq Mtrq MWSPCI Host Data Transfer Complete Master Data TransferredPCI Time Out Termination PCI Target RetryPCI Address Parity Error PCI Data Parity ErrorPCI Target Disconnect PCI Target Abort15. DSP PCI Status Register Dpsr Bit Definitions DSP Receive Data Fifo DrxrPCI Master Wait States PCI Master Receive Data RequestDSP Slave Transmit Data Register Dtxs DSP Master Transmit Data Register DtxmDSP Host Port Gpio Direction Register Dirh DSP Host Port Gpio Data Register Dath16.DATH and Dirh Functionality Host-Side Programming Model 17.HI32 Programming Model, Host-Side RegistersMemory Register Host-Side Programming Model Executed as Command Type 18.PCI Bus CommandsHC3/HBE3-HC0/HBE0 Ignored20. Host-Side Registers PCI Configuration Address Space 21. Host-Side Registers Universal Bus Mode Address Space19. Host-Side Registers PCI Memory Address Space 13.Host Interface Control Register Hctr 1 HI32 Control Register HctrTarget Wait State Disable Bit Bit Name Reset Mode Description Number22.Host Interface Control Register Hctr Bit Definitions Twsd PCIHost Receive Data Transfer Format Host Transmit Data Transfer Format Inserted Address SFT UBMSlave Fetch Type Cleared when the DSP56300 core writes to Universal Bus mode Fetch SFT =Reset, and Strq and Hstrhrrq are cleared Data path is lost when the reset state isDmae UBM Dmae HaenHirq Rreq UBM Receive Req uest EnableDmae Treq Rreq Hirq Pin Hdrq pinHreq Hint HF5 HF4 HF3 Host Interface Status Register HstrTrdy UBM UBM UBM UBM UBM UBM PCI PCI PCI PCI PCI PCIHost Request 23.Host Interface Status Register Hstr Bit DefinitionsHost interrupt a Treq Rreq HreqHost Receive Data Request Host Transmit Data RequestTransmitter Ready 15.Host Command Vector Register Hcvr Host Command Vector Register HcvrHost Command Vector 24.Host Command Vector Register Hcvr Bit DefinitionsBit Bit Name Reset Value Mode Description Number Hnmi UBMWhen the DSP56300 core acknowledges the host command Host CommandHost Master Receive Data Register Hrxm Host Slave Receive Data Register HrxsHost Transmit Data Register Htxr Universal Bus mode Dctrhm = $2 or $3 PCI Mode Dctrhm = $1Status/Command Configuration Register CSTR/CCMR Device ID/Vendor ID Configuration Register CDID/CVIDDPE SSE RMA RTA STA DPR FbbcSignaled System Error Detected Parity ErrorSignalled Target Abort Received Master AbortWait Cycle Control hardwired to zero System Error EnableParity Error Response Bus Master EnableClass Code/Revision ID Configuration Register CCCR/CRID HT7 HT6 HT5 HT4 HT3 HT2 HT1 HT0 Header Type hardwired to $00HT7-0 Read-only bits that identify the layout of bytes $10-$3FLatency Timer High Cache Line SizeCcls Universal Bus Mode Base Address Memory Space Base Address Configuration Register CbmaPM8 PM7 PM6 PM5 PM4 MS1 MS0 MSI Memory Base Address High/LowMemory Base Address Low Hardwired to zeros 29. Memory Space Base Address Configuration Register CbmaPre-Fetch Hardwired to zero Memory Space Hardwired to zerosExample 6-5. Code for Setting the Csid IL5 IL4 Interrupt Line-Interrupt Pin Configuration RegisterCILPIL1 IL0 MaxlatHS PH PS HI32 Programming Model/Quick ReferenceDctr Hcie UBM HrspDpcr Mtie ClrtRble Dpar DpmcDSR HCP HactDper Dpsr AperHdtc RdcqDmae TreqISA/EISA SFTHnmi HcvrHrxm HrxsCccr Ccmr RMAChty Cbma MSIRsma Rsmb Tsma Tclk STD GDB DDB RclkTsmb TX0 CRA SC0Essi Enhancements Serial Transmit Data Signal STD Essi Data and Control SignalsSerial Receive Data Signal SRD Serial Clock SCKSerial Control Signal SC1 Serial Control Signal SC0Mode and Signal Definitions Control Bits Essi SignalsSYN TE0 TE1 TE2 SC0 SC1 SC2 SCK STD SRD Essi After Reset Serial Control Signal SC2Operation InitializationExceptions Operation Write data to all enabled transmit registers Operating Modes Normal, Network, and On-Demand Normal/Network/On-Demand Mode SelectionFrame Sync Signal Format Synchronous/Asynchronous Operating ModesFrame Sync Selection Frame Sync Length for Multiple Devices Word Length Frame Sync and Data Word TimingFrame Sync Polarity Flags Byte Format LSB/MSB for the TransmitterEssi Control Register a CRA Essi Programming ModelWL2 WL1 WL0 ALC PM7 PM6 PM5 PM4 PM3 PM2 PM1 PM0Select SC1 Essi Control Register a CRA Bit DefinitionsWord Length Control Essi Word Length SelectionFrame Rate Divider Control Alignment ControlPrescaler Range Prescale Modulus SelectCrbsyn = CRBTE1 CRBOF0 SSISRIF0Rclock TclockShfd Essi Control Register B CRBOF1 OF0 ESSI0 X$FFFFB6, ESSI1 X$FFFFA6Essi Control Register B CRB Bit Definitions Receive Enable Transmit Interrupt EnableTransmit 0 Enable TIETransmit 2 Enable Transmit 1 EnableMode Select Synchronous/AsynchronousFSL1 FSL0 OF1 Serial Control DirectionSerial Output Flag OF0Serial Clock RX, TX Frame Sync RX, TX Serial Data Serial Clock RX Frame Sync RX Serial DataTX Frame Sync TX Serial Data Essi Bit CRB SYN Bit OperationBit Operation SSI Control Register B CRB READ/WRITEReceiver Interrupt or DMA Request and Flags Set Frame Sync FSL0 = 0, FSL1 = Data Flags Frame Sync FSL0 = 0, FSL1 = Data Out FlagsTransmitter Underrun Error Flag Receiver Overrun Error FlagEssi Status Register Ssisr Receive Data Register FullReceive Frame Sync Flag Essi Receive Shift RegisterTransmit Frame Sync Flag Serial Input FlagEssi Transmit Shift Registers Essi Receive Data Register RXTransmit Registers Receive RegistersWL0 Transmit Middle Byte Transmit Low Byte Register 24 BitLeast Significant MSBEssi Time Slot Register TSR Essi Transmit Data Registers TX2-0Transmit Slot Mask Registers TSMA, Tsmb TS9 TS8 TS7 TS6 TS5 TS4 TS3 TS2 TS1 TS015.ESSI Transmit Slot Mask Register B Tsmb RS7 RS6 Receive Slot Mask Registers RSMA, RsmbRS1 RS0 RS15 RS14 RS13 RS12 RS11 RS10Port Control Registers Pcrc and Pcrd Gpio Signals and RegistersEssi Port Signal Configurations Port Direction Registers Prrc and PrrdESSI0/ESSI1 20.Port Data Registers Pdrc X$FFFFBD Pdrd X $FFFFAD Port Data Registers Pdrc and PdrdSerial Communication Interface SCI Serial Communication Interface SCISynchronous Mode Asynchronous ModeMultidrop Mode Wired-OR Mode I/O SignalsAddress Mode Wakeup Transmitting Data and Address CharactersReceive Data RXD Transmit Data TXDSCI Serial Clock Sclk SCI Registers After Reset SCI After ResetReie Sckp Stir Tmie TIE RIE Ilie Woms RWU Wake SBK SsftdSCI Initialization Preamble, Break, and Data Transmission Priority Exceptions Bootstrap Loading Through the SCI Boot Mode 2 or aSCI Programming Model WDS2 WDS1 WDS0 Bit Synchronous Data Shift Register ModeBit Asynchronous 1 Start, 8 Data, 1 Stop Bit Asynchronous 1 Start, 8 Data, 1 Even Parity, 1 StopSCI Data Word Formats Ssftd = 0 SCI Control Register SCR ReieStir Tmie TIE RIE Ilie Woms RWU Wake SBK Ssftd WDS2 SCI Transmit Interrupt Enable Timer Interrupt EnableSCI Receive Interrupt Enable Idle Line Interrupt EnableReceiver Enable Wired-OR Mode SelectWoms Wakeup Mode Select Receiver Wakeup EnableSend Break SCI Shift DirectionMode Word Formats Word SelectWDS1 WDS0 SCI Status Register SSR SCI Status Register SCI Status Register SSR Bit DefinitionsIdle Rdrf Tdre Trne Idle Line Flag TdreTransmitter Empty TCM RCM SCP COD SCI Clock Control Register SccrTCM RCM SclkDivide by Bit CounterCD11-0 Sckp = 0 + Sckp =X1 Clock X16 Clock Sckp = RX, TX Data Ssftd =SCI Data Registers SCI Receive Register SRXSCI Receive Data Shift Register SCI Transmit Register STX Port E Control Register Pcre PE2 PE1 PE0Sclk TXD RXD Port E Data Register Pdre Port E Direction Register PrrePRRE1 PRRE0 PDRE1 PDRE0Gpio Signals and Registers DSP56301 User’s Manual Triple Timer Module Triple Timer ModuleIndividual Timer Block Diagram Triple Timer Module Block DiagramGDB TpcrTimer Module Block Diagram Timer After ResetTimer Exceptions Timer InitializationTCSR0 Tcie Timer Gpio Mode Triple Timer ModesTC3 TC2 TC1 TC0 TIOMode 0 internal clock, no timer output TRM = TLRTCR Tcpr Timer Pulse Mode Mode 1 internal clock TRM =Output Pulse width = timer clock Period Mode 2 internal clock TRM = 1 first event Timer Toggle ModeToggle Timer = write preload = write compare Clock CLK/2 or prescale CLKMode 2 internal clock TRM = = write preload= write compare Clock CLK/2 or prescale CLK Mode 3 internal clock TRM = Timer Event Counter ModeInput External TIO Cpuclk += write compare Clock 10.Event Counter Mode, TRM =Measurement Input Width Mode Signal Measurement ModesInput Input width MeasurementMode 4 internal clock TRM = 1 first event Mode 4 internal clock TRM =Mode 5 internal clock TRM = Measurement Input Period ModeFirst event = write preload = write compare Input period Measurement InternalCounting, does May occur TOF=1Reads TCR period Mode 6 internal clock TRM = Measurement Capture ModeInterrupt Service reads TCR delay = M N clock periods InternalPulse Width Modulation PWM, Mode PWMPulse width modulation 16.Pulse Width Modulation Toggle Mode, TRM = Mode 7 internal clock TRM =17.Pulse Width Modulation Toggle Mode, TRM = Watchdog Modes Watchdog Pulse ModePulse Watchdog Output InternalMode 9 internal clock TRM = Software does not reset watchdog timer watchdog times out= write preload First event Mode 10 internal clock TRM = Watchdog Toggle ModeWatchdog Output ToggleSpecial Cases Triple Timer Module Programming ModelDMA Trigger Prescaler CounterRegister Tplr Timer Prescaler Load23 22 21 20 19 18 17 Tplr = $FFFF83Prescaler Source Timer Prescaler Load Register TplrPS1 PS0 Prescaler Preload ValueTimer Control/Status Register Tcsr Timer Prescaler Count Register TpcrTCF TOF PCE TRM INVTimer Overflow Flag Timer Compare FlagPrescaler Clock Enable Data OutputTimer Reload Mode DirectionInverter Number Function Timer ControlTimer Overflow Interrupt Enable Timer Compare Interrupt EnableTimer Enable TIO Programmed as Input TIO Programmed as Output Mode INV =Timer Load Register TLR Pulse generated by Timer has Timer has negativePositive polarity Timer Count Register TCR Timer Compare Register TcprAppendix a DSP56301 User’s Manual HBS Can be stopped Hdben Aarv Mscte EQU LOOP0 Lbld Lble LOOP8 LOOP11 Rep Mac x0,x1,a x,lr0+ ORG PL,PL Patterns Write to Destination DSP56301 User’s Manual Programming Reference Chapter BTable B-1.Guide to Programming Sheets Internal I/O Memory Map Table B-2. Internal I/O Memory Map X Data MemoryBit Address Register Name Peripheral Bit Address Register Name Table B-2.Internal I/O Memory Map X Data Memory$FFCC $FFFFCC $FFCD $FFFFCD$FFCB $FFFFCB $FFCA $FFFFCA$FFBB $FFFFBB Essi $FFBC $FFFFBC$FFBA $FFFFBA $FFB9 $FFFFB9$FFAB $FFFFAB Essi $FFAC $FFFFAC$FFAA $FFFFAA $FFA9 $FFFFA9$FFFF91 $FFFF92$FFFF90 $FF8F $FFFF8FTable B-3. Interrupt Sources Interrupt Sources and PrioritiesVBA$6A Table B-3.Interrupt SourcesVBA$6C VBA$6ETable B-4.Interrupt Source Priorities Within an IPL Nonmaskable Host Command InterruptESSI0 receive last slot interrupt Figure B-1.Status Register SR Programming SheetsStop Delay External Bus DisableMemory Switch Mode Burst Mode EnableIrqc Mode Irqd ModeIrqb Mode Irqa ModeTriple Timer IPL Host IPLInterrupt Priority Register Iprp $FFFFFE Read/Write Crystal Range Bit Xtlr PLL Control Register Pctl $FFFFFD Read/WriteBus Control Register BCR $FFFFFB Read/Write Default Area Wait Control, BitsBus Request Hold, Bit Bus Lock Hold, BitDram Control Register DCR $FFFFFA Read/Write Bus Y Data Memory Enable, Bit Bus Packing Enable, BitBus X Data Memory Enable, Bit Bus Program Memory Enable, BitDMA Control Registers DCR5-DCR0 Reset = $000000 $FFFFE4, X$FFFFE8, X$FFFFEC Read/WriteApplication DSP Control Register Dctr Read/Write Address X FFFFC5DSP PCI Control Register Dpcr Address XFFFFC6 Read/Write = Enables master receive interruptsFigure B-12.DSP PCI Master Control Register Dpmc Figure B-13.DSP PCI Address Register Dpar PCI Bus Command, BitsHI32 Control Register Hctr Read/Write Host Non-Maskable Interrupt, Bit HI32 Command Vector Register Hcvr Read/WriteSignaled System Error, Bit Detected Parity Error, BitSignalled Target Abort, Bit System Error Enable, BitRead/Write Latency Timer High, BitsHeader Type, Bits Cache Line Size, BitsReset = $00000000 HI32 Memory Space Base Address Configuration Register CbmaPCI Mode Base Address High, Bits Pre-fetch, Bit Memory Space Indicator, BitSubsystem ID Register, Bits 31-16 Specifies the subsystem ID ESSI1-X$FFFFA5 Read/Write Essi Control Register a CRAx ESSI0-X$FFFFB5 Read/WriteEssi Control Register B CRBx ESSI0-X$FFFFB6 Read/WriteESSI1-X$FFFFA6 Read/Write ESSI1-X$FFFFA4 Read/Write Essi Transmit Slot Mask a TSMA0-1 ESSI0-X$FFFFB4 Read/WriteEssi Transmit Slot Mask B TSMB0-1 ESSI0-X$FFFFB3 Read/Write ESSI1-X$FFFFA3 Read/WriteSCI Control Register SCR $FFFF9C Read/Write SCI Clock Control Register Sccr Address X$FFFF9B Read/Write Receiver Clock Mode/SourceClock Out Divider Timer Prescaler Load Register Tplr $FFFF83 Read/Write Figure B-25.Timer Prescaler Load Register TplrTCSR1$FFFF8B Read/Write TCSR2$FFFF87 Read/Write Timer Control/Status Register TCSR0$FFFF8F Read/WriteTLR1-X$FFFF8A Write Only TLR2-X$FFFF86 Write Only Timer Load Register TLR0-2 TLR0-X$FFFF8E Write OnlyPort B HI08 Host Data Direction Register Hddr X$FFFFC8 WriteHost Data Register HDR $FFFFC9 Write Port C Control Register Pcrc $FFFFBF Read/Write Port C ESSI0Port C Direction Register Prrc $FFFFBE Read/Write Port C Gpio Data Register Pdrc $FFFFBD Read/WritePort D Control Register Pcrd $FFFFAF Read/Write Port D ESSI1Port D Direction Register Prrd $FFFFAE Read/Write Port D Gpio Data Register Pdrd $FFFFAD Read/WritePort E Control Register Pcre $FFFF9F Read/Write Port E SCIPort E Direction Register Prre $FFFF9E Read/Write Port E Gpio Data Register Pdre $FFFF9D Read/WriteProgramming Sheets DSP56301 User’s Manual Index Index-2 DSP56301 User’s Manual Index-3 Index-4 DSP56301 User’s Manual Index-5 Index-6 DSP56301 User’s Manual Index-7 Index-8 DSP56301 User’s Manual Index-9 Index-10 DSP56301 User’s Manual Index-11 Index-12 DSP56301 User’s Manual Index-13 Index-14 DSP56301 User’s Manual Index-15 Index-16 DSP56301 User’s Manual

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mac x0,x1,a x,l:(r0)+

DSP56301 User’s Manual

DSP56301 specifications