Motorola DSP56301 user manual Bus Release Timing, Synchronize Select, Cache Burst Mode Enable

Central Processor Unit (CPU) Registers

Table 4-4.Operating Mode Register (OMR) Bit Definitions (Continued)

Bit Number	Bit Name	Reset Value			Description
12	BRT	0	Bus Release Timing
			Selects between fast or slow bus release. If BRT is cleared, a Fast Bus
			Release mode is selected (that is, no additional cycles are added to the
			access and BB is not guaranteed to be the last Port A pin that is tri-stated
			at the end of the access). If BRT is set, a Slow Bus Release mode is
			selected (that is, an additional cycle is added to the access, and BB is the
			last Port A pin that is tri-stated at the end of the access).
11	TAS	0		Synchronize Select
			TA
			Selects the synchronization method for the input Port A pin—TA					(Transfer
			Acknowledge). If TAS is cleared, you are responsible for asserting the TA
			pin in synchrony with the chip clock, as described in the technical data
			sheet. If TAS is set, the TA input pin is synchronized inside the chip, thus
			eliminating the need for an off-chip synchronizer.
			Note:
					The TAS bit has no effect when the	TA	pin is deasserted: you are
					responsible for deasserting the TA pin in synchrony with the chip
					clock, regardless of the value of TAS.
10	BE	0	Cache Burst Mode Enable
			Enables/disables Burst mode in the memory expansion port during an
			instruction cache miss. If the bit is cleared, Burst mode is disabled and
			only one program word is fetched from the external memory when an
			instruction cache miss condition is detected. If the bit is set, Burst mode is
			enabled, and up to four program words are fetched from the external
			memory when an instruction cache miss is detected.
9–8	CDP[1–0]	11	Core-DMA Priority
			Specify the priority of core and DMA accesses to the external bus.
			ν 00 = Determined by comparing status register CP[1–0] to the active
				DMA channel priority
			ν 01 = DMA accesses have higher priority than core accesses
			ν 10 = DMA accesses have the same priority as the core accesses
			ν 11 = DMA accesses have lower priority than the core accesses
7	MS	0	Memory Switch Mode
			Allows some internal data memory (X, Y, or both) to become part of the
			chip internal Program RAM.
			Notes:		1. Program data placed in the Program RAM/Instruction Cache
					area changes its placement after the OMR[MS] bit is set
					(that is, the Instruction Cache always uses the lowest
					internal Program RAM addresses).
					2. To ensure proper operation, place six NOP instructions after
					the instruction that changes the MS bit.
					3. To ensure proper operation, do not set the MS bit while the
					Instruction Cache is enabled (SR[CE] bit is set).

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