Host Interface Status Register Hstr, Trdy

Host-Side Programming Model

Table 6-22.Host Interface Control Register (HCTR) Bit Definitions (Continued)

Bit	Bit Name	Reset	Mode			Description
Number	Bit Name	Value	Mode			Description
Number		Value


1	TREQ	0	UBM	Transmit Request Enable
				Controls the HIRQ and HDRQ pins for host transmit data transfers in a
				Universal Bus mode (DCTR[HM] = $2 or $3). When the DMA enable bit
				(DMAE) is cleared, TREQ (when set) enables the Host Interrupt Request
				HIRQ pin if the host transmit data request (HTRQ) status bit in the HI32
				Status Register (HSTR) is set. If TREQ is cleared, HTRQ host interrupt
				requests are disabled. If TREQ is set and HTRQ is set, the host interrupt
				request	HIRQ	pin is asserted. HDRQ is deasserted.
				When DMAE and the HSTR[HTRQ] status bit are set, TREQ enables the
				host DMA request (HDRQ) pin. When TREQ is cleared, HTRQ external
				DMA requests are disabled. If TREQ and HTRQ are set, the host DMA
				request HDRQ pin is asserted. HIRQ is deasserted (high impedance if
				HIRD = 0 in the DCTR). The personal hardware reset clears TREQ.

0		0		Reserved. Write to zero for future compatibility.

Note: 1.	High impedance if HIRD = 0 in the DCTR.
2.	High impedance if HIRD = 0 in the DCTR.

6.8.2Host Interface Status Register (HSTR)

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8		7	6	5	4	3	2	1	0

								HREQ		HINT	HF5	HF4	HF3	HRRQ	HTRQ	TRDY

								UBM		UBM	UBM	UBM UBM UBM UBM UBM
									PCI	PCI	PCI	PCI PCI PCI PCI PCI
	Reserved, read as zero and should be written zero								UBM = Universal Bus mode PCI = PCI mode
	Reserved, read as zero and should be written zero								UBM = Universal Bus mode PCI = PCI mode

Figure 6-14.Host Interface Status Register (HSTR)

The HSTR is a 32-bit read-only status register by which the host processor examines the status and flags of the HI32.

νWhen the HSTR is read to the PCI bus (DCTR[HM] = $1), the HAD[31– 0] pins are driven with the HSTR data during a read access.

νIn a 24-bit data Universal Bus mode (DCTR[HM] = $2 or $3 and HCTR[HRF] = $0), the HD[23–0] pins are driven with the three least significant HSTR bytes during a read access.

6-56	DSP56301 User’s Manual

DSP56301 specifications

The Motorola DSP56301 is a highly efficient digital signal processor, specifically engineered for real-time audio and speech processing applications. This DSP is part of Motorola's renowned DSP56300 family, which is recognized for its innovative features and outstanding performance in the realm of digital signal processing.

One of the main features of the DSP56301 is its ability to handle complex computations at high speeds. With a maximum clock frequency of 66 MHz, it delivers fast performance, enabling it to process audio signals in real time. The chip is built on a 24-bit architecture, which allows for high-resolution audio processing. This is particularly beneficial in applications such as telecommunications, consumer audio devices, and professional audio equipment, where precision is paramount.

The DSP56301 boasts a comprehensive instruction set that includes efficient mathematical operations, which are essential for digital filters and audio effects processing. One of the key innovations of this device is its dual data path architecture, which permits simultaneous processing of multiple data streams. This feature significantly enhances the device's throughput and responsiveness, making it suitable for demanding applications such as voice recognition and synthesis.

In terms of memory regions, the DSP56301 includes several on-chip memory categories, such as program memory, data memory, and a specialized memory for coefficients. The architecture's support for external memory expansion further increases its versatility, allowing designers to tailor systems to their specific requirements.

The DSP56301 implements advanced features such as a powerful on-chip hardware multiplier and accumulator, simplifying complex mathematical tasks and accelerating the execution of algorithms. Its flexible interrupt system enhances its capability to respond to time-sensitive operations, while the integrated serial ports facilitate efficient data communication with external devices.

Power consumption is also a vital characteristic of the DSP56301. It is designed with energy efficiency in mind, allowing for extended operation in battery-powered devices. The chip’s low power requirements are particularly advantageous in portable audio devices and other applications where energy conservation is crucial.

In conclusion, the Motorola DSP56301 is an exceptional digital signal processor that combines high processing power, flexibility, and efficiency. Its main features, advanced technologies, and robust architecture make it a top choice for developers seeking to create sophisticated audio and signal processing systems. With its enduring legacy in the industry, the DSP56301 continues to be relevant in a variety of modern applications, ensuring it remains a valuable tool for engineers and designers.

Motorola DSP56301 user manual Host Interface Status Register Hstr, Hreq Hint HF5 HF4 HF3, Trdy

Models: DSP56301

Host-Side Programming Model

Table 6-22.Host Interface Control Register (HCTR) Bit Definitions (Continued)

Bit

Mode

Transmit Request Enable

HIRQ

6.8.2Host Interface Status Register (HSTR)

HREQ

HINT

HF5

HF4

HF3

TRDY

UBM

UBM UBM UBM UBM UBM

PCI

PCI PCI PCI PCI PCI

Figure 6-14.Host Interface Status Register (HSTR)

DSP56301 specifications