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Motorola DSP56301 user manual Inserted Address, Sft Ubm, Slave Fetch Type

Models: DSP56301

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Host-Side Programming Model

Table 6-22.Host Interface Control Register (HCTR) Bit Definitions (Continued)

Bit

Bit Name

Reset

Mode

 

 

 

 

Description

Number

Value

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

9–8

HTF[1–0]

0

UBM

Host Transmit Data Transfer Format (cont.)

cont.

 

 

PCI

Note:

When the HI32 is in PCI mode, the HTF control bits affect the

 

 

 

 

 

 

address insertion (the IAE bit is set in the DPCR) in the same

 

 

 

 

 

 

way they affect the transferred data.

 

 

 

 

Address as appears on the PCI bus: $12345678

 

 

 

 

 

 

 

 

 

 

 

 

HTF[1–0]

 

Inserted Address

 

 

 

 

 

 

 

 

 

 

 

 

 

0

 

0

$005678, $001234

 

 

 

 

 

 

 

 

 

 

 

 

0

 

1

$345678

 

 

 

 

 

 

 

 

 

 

 

 

1

 

0

$345678

 

 

 

 

 

 

 

 

 

 

 

 

1

 

1

$123456

 

 

 

 

 

 

 

 

7

SFT

0

UBM

Slave Fetch Type

 

 

 

 

PCI

Defines Fetch mode (data fetch or pre-fetch), as follows:

 

 

 

 

ν SFT = 1, Fetch

 

 

 

 

 

ν SFT = 0, Pre-Fetch

 

 

 

 

In Fetch mode, the HI32 requests data from the DSP56300 core only

 

 

 

 

after the host has begun a read transaction from the HI32. The HI32

 

 

 

 

issues this request by enabling the STRQ status bit and generating core

 

 

 

 

interrupt requests or DMA requests, if enabled. In Pre-Fetch mode: the

 

 

 

 

HI32 requests data from the DSP56300 core whenever the DTXS is not

 

 

 

 

full. The HI32 issues this request by enabling the STRQ status bit and

 

 

 

 

generating core interrupt requests or DMA requests, if enabled. The

 

 

 

 

value of SFT can be changed only if the DTXS-HRXS data path is empty.

 

 

 

 

The personal hardware reset clears SFT.

 

 

 

 

 

 

 

 

 

 

 

PCI mode

 

Fetch (SFT = 1):

 

 

 

 

(DCTR[HM] = $1)

The DSP-to-host data path (DTXS-HRXS) is a six

 

 

 

 

 

 

 

 

word deep (three word deep if HCTR[HRF] = $0)

 

 

 

 

 

 

 

 

FIFO buffer. Writing SFT = 1 resets the

 

 

 

 

 

 

 

 

DSP-to-host data path and clears STRQ and

 

 

 

 

 

 

 

 

HSTR[HRRQ]. During a read transaction from the

 

 

 

 

 

 

 

 

HRXS, STRQ is set if the DTXS-HRXS FIFO is

 

 

 

 

 

 

 

 

not full, and cleared when the DSP56300 core fills

 

 

 

 

 

 

 

 

the DTXS. HSTR[HRRQ] is cleared if the HRXS

 

 

 

 

 

 

 

 

is empty, and set if it contains data to be read by

 

 

 

 

 

 

 

 

an external host. If the host is not executing a

 

 

 

 

 

 

 

 

read transaction from the HRXS, the DSP-to-host

 

 

 

 

 

 

 

 

data path is forced to the reset state and STRQ

 

 

 

 

 

 

 

 

and HSTR[HRRQ] are cleared.

 

 

 

 

 

 

 

 

 

6-52

DSP56301 User’s Manual

Page 169 Page 171
Page 170
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Motorola DSP56301 user manual Inserted Address, Sft Ubm, Slave Fetch Type
Page 169 Page 171

DSP56301 specifications

The Motorola DSP56301 is a highly efficient digital signal processor, specifically engineered for real-time audio and speech processing applications. This DSP is part of Motorola's renowned DSP56300 family, which is recognized for its innovative features and outstanding performance in the realm of digital signal processing.

One of the main features of the DSP56301 is its ability to handle complex computations at high speeds. With a maximum clock frequency of 66 MHz, it delivers fast performance, enabling it to process audio signals in real time. The chip is built on a 24-bit architecture, which allows for high-resolution audio processing. This is particularly beneficial in applications such as telecommunications, consumer audio devices, and professional audio equipment, where precision is paramount.

The DSP56301 boasts a comprehensive instruction set that includes efficient mathematical operations, which are essential for digital filters and audio effects processing. One of the key innovations of this device is its dual data path architecture, which permits simultaneous processing of multiple data streams. This feature significantly enhances the device's throughput and responsiveness, making it suitable for demanding applications such as voice recognition and synthesis.

In terms of memory regions, the DSP56301 includes several on-chip memory categories, such as program memory, data memory, and a specialized memory for coefficients. The architecture's support for external memory expansion further increases its versatility, allowing designers to tailor systems to their specific requirements.

The DSP56301 implements advanced features such as a powerful on-chip hardware multiplier and accumulator, simplifying complex mathematical tasks and accelerating the execution of algorithms. Its flexible interrupt system enhances its capability to respond to time-sensitive operations, while the integrated serial ports facilitate efficient data communication with external devices.

Power consumption is also a vital characteristic of the DSP56301. It is designed with energy efficiency in mind, allowing for extended operation in battery-powered devices. The chip’s low power requirements are particularly advantageous in portable audio devices and other applications where energy conservation is crucial.

In conclusion, the Motorola DSP56301 is an exceptional digital signal processor that combines high processing power, flexibility, and efficiency. Its main features, advanced technologies, and robust architecture make it a top choice for developers seeking to create sophisticated audio and signal processing systems. With its enduring legacy in the industry, the DSP56301 continues to be relevant in a variety of modern applications, ensuring it remains a valuable tool for engineers and designers.