Triple Timer Module Programming Model

Table 9-3.Timer Control/Status Register (TCSR) Bit Definitions (Continued)

Bit Number

Bit Name

Reset Value

Description

 

 

 

 

 

 

 

 

11

DIR

0

Direction

 

 

 

Determines the behavior of the TIO signal when it functions as a GPIO

 

 

 

signal. When DIR is set, the TIO signal is an output; when DIR is cleared,

 

 

 

the TIO signal is an input. The TIO signal functions as a GPIO signal only

 

 

 

when the TC[3–0] bits are cleared. If any of the TC[3–0] bits are set, then

 

 

 

the GPIO function is disabled, and the DIR bit has no effect.

 

 

 

 

10

 

0

Reserved. Write to zero for future compatibility.

 

 

 

 

9

TRM

0

Timer Reload Mode

 

 

 

Controls the counter preload operation. In timer (0–3) and watchdog

 

 

 

(9–10) modes, the counter is preloaded with the TLR value after the

 

 

 

TCSR[TE] bit is set and the first internal or external clock signal is

 

 

 

received. If the TRM bit is set, the counter is reloaded each time after it

 

 

 

reaches the value contained by the TCR. In PWM mode (7), the counter is

 

 

 

reloaded each time counter overflow occurs. In measurement (4–5)

 

 

 

modes, if the TRM and the TCSR[TE] bits are set, the counter is preloaded

 

 

 

with the TLR value on each appropriate edge of the input signal. If the

 

 

 

TRM bit is cleared, the counter operates as a free running counter and is

 

 

 

incremented on each incoming event.

 

 

 

 

8

INV

0

Inverter

 

 

 

Affects the polarity definition of the incoming signal on the TIO signal when

 

 

 

TIO is programmed as input. It also affects the polarity of the output pulse

 

 

 

generated on the TIO signal when TIO is programmed as output. See

 

 

 

Table 9-4, “Inverter (INV) Bit Operation,” on page 32. The INV bit does not

 

 

 

affect the polarity of the prescaler source when the TIO is input to the

 

 

 

prescaler.

 

 

 

NOTE: The INV bit affects both the timer and GPIO modes of operation.

 

 

 

To ensure correct operation, change this bit only when one or both of the

 

 

 

following conditions is true: the timer is disabled (the TCSR[TE] bit is

 

 

 

cleared). The timer is in GPIO mode.

 

 

 

 

9-30

DSP56301 User’s Manual

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Motorola DSP56301 user manual Direction, Timer Reload Mode, Inverter
Page 291 Page 293

DSP56301 specifications

The Motorola DSP56301 is a highly efficient digital signal processor, specifically engineered for real-time audio and speech processing applications. This DSP is part of Motorola's renowned DSP56300 family, which is recognized for its innovative features and outstanding performance in the realm of digital signal processing.

One of the main features of the DSP56301 is its ability to handle complex computations at high speeds. With a maximum clock frequency of 66 MHz, it delivers fast performance, enabling it to process audio signals in real time. The chip is built on a 24-bit architecture, which allows for high-resolution audio processing. This is particularly beneficial in applications such as telecommunications, consumer audio devices, and professional audio equipment, where precision is paramount.

The DSP56301 boasts a comprehensive instruction set that includes efficient mathematical operations, which are essential for digital filters and audio effects processing. One of the key innovations of this device is its dual data path architecture, which permits simultaneous processing of multiple data streams. This feature significantly enhances the device's throughput and responsiveness, making it suitable for demanding applications such as voice recognition and synthesis.

In terms of memory regions, the DSP56301 includes several on-chip memory categories, such as program memory, data memory, and a specialized memory for coefficients. The architecture's support for external memory expansion further increases its versatility, allowing designers to tailor systems to their specific requirements.

The DSP56301 implements advanced features such as a powerful on-chip hardware multiplier and accumulator, simplifying complex mathematical tasks and accelerating the execution of algorithms. Its flexible interrupt system enhances its capability to respond to time-sensitive operations, while the integrated serial ports facilitate efficient data communication with external devices.

Power consumption is also a vital characteristic of the DSP56301. It is designed with energy efficiency in mind, allowing for extended operation in battery-powered devices. The chip’s low power requirements are particularly advantageous in portable audio devices and other applications where energy conservation is crucial.

In conclusion, the Motorola DSP56301 is an exceptional digital signal processor that combines high processing power, flexibility, and efficiency. Its main features, advanced technologies, and robust architecture make it a top choice for developers seeking to create sophisticated audio and signal processing systems. With its enduring legacy in the industry, the DSP56301 continues to be relevant in a variety of modern applications, ensuring it remains a valuable tool for engineers and designers.
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