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Motorola DSP56301 user manual Enhanced Synchronous Serial Interface, PC0, PC1, PC2

Models: DSP56301

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Enhanced Synchronous Serial Interface 0

Table 2-13.Enhanced Synchronous Serial Interface 0

	Signal Name	Type	State During	Signal Description
	Signal Name	Type	Reset	Signal Description
			Reset


	SC00	Input or Output	Input	Serial Control 0—For asynchronous mode, this signal is
				used for the receive clock I/O (Schmitt-trigger input). For
				synchronous mode, this signal is used either for transmitter 1
				output or for serial I/O flag 0.
				Port C 0—The default configuration following reset is GPIO
				input PC0. When configured as PC0, signal direction is
				controlled through the port directions register (PRR0). The
	PC0			signal can be configured as ESSI signal SC00 through the
				port control register (PCR0).
				This signal has a weak keeper to maintain the last state even
				if all drivers are tri-stated.

	SC01	Input/	Input	Serial Control 1—For asynchronous mode, this signal is the
		Output		receiver frame sync I/O. For synchronous mode, this signal is
				used either for transmitter 2 output or for serial I/O flag 1.
				Port C 1—The default configuration following reset is GPIO
				input PC1. When configured as PC1, signal direction is
	PC1	Input or Output		controlled through PRR0. The signal can be configured as an
				ESSI signal SC01 through PCR0.
				This signal has a weak keeper to maintain the last state even
				if all drivers are tri-stated.

	SC02	Input/	Input	Serial Control Signal 2—Used for frame sync I/O. SC02 is
		Output		the frame sync for both the transmitter and receiver in
				synchronous mode, and for the transmitter only in
				asynchronous mode. When configured as an output, this
				signal is the internally generated frame sync signal. When
				configured as an input, this signal receives an external frame
				sync signal for the transmitter (and the receiver in
				synchronous operation).
				Port C 2—The default configuration following reset is GPIO
	PC2	Input or Output		input PC2. When configured as PC2, signal direction is
				controlled through PRR0. The signal can be configured as an
				ESSI signal SC02 through PCR0.
				This signal has a weak keeper to maintain the last state even
				if all drivers are tri-stated.

Signals/Connections

2-23

Image 53

Motorola DSP56301 user manual Enhanced Synchronous Serial Interface, PC0, PC1, PC2

Contents

Revision 3, March DSP56301 User’s ManualUSA/EUROPE How to reach usJapan ASIA/PACIFICPage Page Contents Chapter Core Configuration Chapter Memory ConfigurationChapter Host Interface HI32 Chapter Programming the PeripheralsChapter Enhanced Synchronous Serial Interface Essi Chapter Serial Communication Interface SCI Index Chapter Triple Timer ModuleChapter a Bootstrap Program Chapter B Programming Reference DSP56301 User’s Manual FiguresXii Pulse Width Modulation Toggle Mode, TRM = DSP Control Register Dctr DSP PCI Control Register Dpcr Tables TablesEssi Clock Sources Overview Manual OrganizationSignal/Symbol Logic State Signal State Voltage High True/Low True Signal ConventionsManual Conventions Ground2PIN is a generic term for any pin on the chip GroundDSP56300 Core Features Size Cache Program RAM Instruction Data RAM Switch Size Cache SizeCE = MS = Data ALU DSP56300 Core Functional BlocksMultiplier-Accumulator MAC Address Generation Unit AGUData ALU Registers Program Control Unit PCU Jtag TAP and OnCE Module PLL and Clock OscillatorOn-Chip Memory DSP56301 Switch Memory ConfigurationInternal Buses Expansion Area DMAMemory Expansion Area Peripherals General-Purpose Input/Output Gpio signalsHost Interface HI32 Enhance Synchronous Serial Interface EssiSerial Communications Interface SCI Triple Timer ModuleDSP56301 Documentation Related Documents and Web SitesName Description Order Number DSP56300FM/ADTimers JTAG/OnCE Port DSP56301 Functional Signal GroupingsEnhanced Synchronous Serial Interfaces ESSI0 ESSI1Port a See -2for a listing of the Host Interface/Port B SignalsDSP56301 Host Interface/Port B Detail Signal Diagram Power Inputs PowerGround Signals GroundPhase-Lock Loop Signals Clock SignalsClock PLLExternal Address Bus External Memory Expansion Port Port aExternal Data Bus External Bus ControlArbitration is reset to the bus slave state Signals are tri-statedOutput Tri-stated Is an active-low output that is Output Tri-stated Is asserted for half a clockBclk CASInterrupt and Mode Control Interrupt and Mode ControlSignal State Type During Signal Description Name Nonmaskable Interrupt-After10.Host Interface Host Interface HI32Command 0-3/Byte Enable 0-3 -When the HI32 is programmed Hpar HBSHdak HperrHirq HserrHstop HWRSignal PCI Mode Enhanced Universal Bus Mode Gpio Mode Name 11.Summary of HI32 Signals and ModesHAD10 HD2 HIO10 HP8 HAD8 HD0 HIO8 HP9 HAD9 HD1 HIO9HAD11 HD3 HIO11 HAD12 HD4 HIO12Gpio 12.Host Port Pins HI32PCI Host Target Ready Host Data Bus Enable Bus Command/Byte Enable Host Address BusReserved Host Initiator Ready Host Data Bus DirectionBus Grant Host Address Enable Parity Error DMA RequestHost Device Select Host Select Acknowledge Host Lock Bus StrobeBus Request Host Transfer Acknowledge Host System Error Host Interrupt RequestHreq is deasserted in the same PCI HstrHost Stop Host Write/Read-Write Hstop HWR/HRWHRD/HDS Initialization Device Select Host Read/Data StrobeAddress/Data Multiplexed Bus Data Bus Host Bus ClockEnhanced Synchronous Serial Interface Hardware ResetHost Interrupt a Active low, open drain output pinPC0 13.Enhanced Synchronous Serial InterfacePC1 PC2PC3 SCK0SRD0 PC4PD0 14.Enhanced Serial Synchronous InterfacePD1 PD2PD3 SCK1SRD1 PD415.Serial Communication Interface TimersSerial Communications Interface SCI Timer 0 Schmitt-Trigger Input/Output- When Timer 16.Triple Timer SignalsTimer 1 Schmitt-Trigger Input/Output- When Timer Timer 2 Schmitt-Trigger Input/Output- When timer17.JTAG/OnCE Interface Signal Name Type State During Signal Description ResetJtag and OnCE Interface Jtag and OnCE Interface DSP56301 User’s Manual Program Memory Space Memory ConfigurationInstruction Cache Memory Switch Modes-Program MemoryInternal Program Memory Memory Switch Modes-X Data Memory Program Bootstrap ROMMemory Configuration Data Memory SpaceInternal Y Data Memory Memory Switch Modes-Y Data MemoryInternal I/O Space-X Data Memory External I/O Space-Y Data Memory Dynamic Memory Configuration SwitchingInternal Memory Configuration Summary Sixteen-Bit Compatibility Mode ConfigurationDSP56301 RAM Configurations DSP56301 RAM Address Ranges by ConfigurationRAM DefaultMemory Maps None 64K $000-$FFF $000-$7FF 16-Bit Space With Default RAM 0, 0$000-$800 $000-$BFF 16MNone 64K $000-$7FF $000-$BFF 16-Bit Space With Switched Program RAM 0, 1$000-$BFF $000-$7FF Not addressable Instruction Cache Enabled 1, 016-Bit Space With Instruction Cache Enabled 1, 0 $000-$3FF $000-$BFF Not addressable Addressable$0400 $0000 Core Configuration Core ConfigurationOperating Modes Reset Description VectorDSP56301 Operating Modes ModeMode Description Operating Mode DefinitionsDSP Clkout rate must be 5/3 of the PCI clock Address attributes selected defaultLow. The DSP56301 is written with 24-bit-wide words Bootstrap Program Status Register SR Central Processor Unit CPU RegistersDMA OMR Sixteen-Bit Arithmetic Mode Cache EnableDo Forever Flag Do Loop FlagSixteen-Bit Compatibility Mode Scaling Rounding Bit SEquation Mode Scaling ModeInterrupt Mask Priority Exceptions Exceptions Masked PermittedScaling Mode Integer Portion Bit Number Bit Name Reset Value Description LimitExtension UnnormalizedOperating Mode Register OMR Bit Definitions Operating Mode Register OMRStack Extension Enable Stack Extension Wrap FlagAddress Attribute Priority Disable Address Trace EnableAsynchronous Bus Arbitration Enable Stack Extension Overflow FlagMemory Switch Mode Cache Burst Mode EnableBus Release Timing Synchronize SelectBit Number Bit Name Reset Value Description Stop Delay Mode Configuring InterruptsExternal Bus Disable Chip Operating ModeInterrupt Priority Registers Iprc and Iprp Interrupt Sources Interrupt Table Memory MapInterrupt Priority Level Bits VBA$1C VBA$1AVBA$1E VBA$2APriority Interrupt Source Processing Interrupt Source Priorities Within an IPLInterrupt Source Priorities Within an IPL TIMER0 overflow interrupt Host command interruptTIMER0 compare interrupt TIMER1 overflow interruptPLL Control Register Pctl Bit Definitions PLL Control Register PctlBus Control Register Bus Interface Unit BIU RegistersBus Area 3 Wait State Control Bus Default Area Wait State ControlBus Area 2 Wait State Control Bus Area 1 Wait State ControlBRP BRF7 BRF6 Dram Control Register DCRBRF3 BRF2 BRF1 Bstr Bren BME Bple BPS110.DRAM Control Register DCR Bit Definitions Bus Dram Page Size Bus Page Logic EnableBus Row Out-of-page Wait States Bus Column In-Page Wait StateBus Number of Address Bits to Compare Address Attribute Registers AAR0-3Bus Address to Compare Bus Y Data Memory Enable Bus Packing EnableBus X Data Memory Enable Bus Program Memory EnableDIE DTM2 DTM1 DTM0 DMA Control Registers 5-0 DCR5-0Dcon DAM5 DAM4 DAM3 DAM2 DAM1 DAM0DMA Transfer Mode DMA Interrupt EnableDTM2-0 Trigger Cleared Transfer Mode After 12.DMA Control Register DCR Bit DefinitionsDMA Channel Priority Number ValueDMA address generation logic, buses, and so forth DPR1-0 Channel PriorityDcon DMA Continuous Mode EnableOMR CDP1-0 CP1-0 Core Priority DRS4-0 Requesting Device Three-Dimensional ModeDMA Request Source DSS1 DSS0 Device Identification Register IDRDDS1 DDS0 Jtag Boundary Scan Register BSR Jtag Identification ID RegisterVersion Information Design Center Number Identity See NoteJtag Boundary Scan Register BSR DSP56301 User’s Manual Programming the Peripherals Peripheral Initialization StepsData Transfer Methods Mapping the Control RegistersPolling Data MemoryInterrupts Advantages and Disadvantages General-Purpose Input/Output Gpio3 DMA Host Interface/Port B Detail Signal Diagram Port B Signals and RegistersPort E Signals and Registers Port C Signals and RegistersPort D Signals and Registers Timer Gpio Triple Timer Signals and RegistersGeneral-Purpose Input/Output Gpio DSP56301 User’s Manual Host Interface HI32 FeaturesHI32 Features, Core-Side and Host-Side HI32 Features in PCI Mode and Universal Bus Mode Overview DSP-Side Registers PCI Configuration SpaceDSP DMA Data Bus DSP Global Data Bus Data transfer format converterHost-to-DSP Data Path Data Transfer PathsDSP-To-Host Data Path Dpmc HI32 PCI Master Data Transfer FormatsFC1 FC0 Two least significant bytes of two HrxmHTF1 HTF0 Transmit Data Transfer FormatHctr DSP to Host Data Transfer Format Receive Transfer Data FormatsHRF Three least significant Hrxs bytesReceive Transfer Data Formats Type Entered when Description Reset StatesDSP-Side Operating Modes HRST/HRSTPCI Mode Dctrhm = $1 Terminate and Reset Dctrhm = $0HI32 Mode PCIExample 6-1. PCI /DMA Throughput 32-Bit Multfactor Self-Configuration Mode Dctrhm = $5 Gpio Mode Dctrhm = $4Example 6-3. Self-Configuration Procedure for PCI Mode Host Port Pin Functionality Host Port PinsPCI Bus Universal Bus Mode DSP56301 ISA Slave MasterHI32 Programming Model, DSP Side Memory Register Address ModeHI32 DSP-Side Programming Model Bit Number Bit Name Mode Description ValueDSP Control Register Dctr 10.DSP Control Register Dctr Bit Definitions Htap Host Data Strobe ModeHost Transfer Acknowledge Polarity Host Read/Write PolaritySlave Transmit Interrupt Enable Slave Receive Interrupt EnableHost Command Interrupt Enable DSP PCI Control Register DpcrReceive Buffer Lock Enable Insert Address Enable11.DSP PCI Control Register Dpcr Bit Definitions IAEMaster Access Counter Enable Master Wait State DisableForce HserrTransaction Termination Interrupt Enable Transfer Complete Interrupt EnableTransaction Abort Interrupt Enable Parity Error Interrupt EnableBL1 BL0 DSP PCI Master Control Register DpmcBL4 Data Transfer Format Control 12.DSP PCI Master Control Register Dmpc Bit DefinitionsA PCI DSP-to-Host transaction A PCI Host-to-DSP transactionDSP PCI Transaction Address High PCI Data Burst Length13.DSP PCI Address Register Dpar Bit Definitions DSP PCI Address Register DparBE2 BE1 AR9 AR8 AR7 AR6 AR5 AR4 AR3 AR2 AR1 AR0C3-0 Command Type PCI Bus CommandDSP PCI Transaction Address Low AR1 AR0DSP Status Register DSR Bit Bit Name Reset Mode Description Number Value14.DSP Status Register DSR Bit Definitions 2322212019181716Slave Receive Data Request Srrq UBMHost Command Pending Mode Description Number Value14. DSP Status Register DSR Bit Definitions Slave Transmit Data Request15.DSP PCI Status Register Dpsr Bit Definitions DSP PCI Status Register DpsrRdcq MDT Hdtc Trty Tdis TAB MAB Aper Marq Mrrq Mtrq MWSPCI Host Data Transfer Complete Master Data TransferredPCI Time Out Termination PCI Target RetryPCI Address Parity Error PCI Data Parity ErrorPCI Target Disconnect PCI Target Abort15. DSP PCI Status Register Dpsr Bit Definitions DSP Receive Data Fifo DrxrPCI Master Wait States PCI Master Receive Data RequestDSP Slave Transmit Data Register Dtxs DSP Master Transmit Data Register Dtxm16.DATH and Dirh Functionality DSP Host Port Gpio Direction Register DirhDSP Host Port Gpio Data Register Dath Memory Register Host-Side Programming Model17.HI32 Programming Model, Host-Side Registers Host-Side Programming Model Executed as Command Type 18.PCI Bus CommandsHC3/HBE3-HC0/HBE0 Ignored19. Host-Side Registers PCI Memory Address Space 20. Host-Side Registers PCI Configuration Address Space21. Host-Side Registers Universal Bus Mode Address Space 13.Host Interface Control Register Hctr 1 HI32 Control Register HctrTarget Wait State Disable Bit Bit Name Reset Mode Description Number22.Host Interface Control Register Hctr Bit Definitions Twsd PCIHost Receive Data Transfer Format Host Transmit Data Transfer Format Slave Fetch Type Inserted AddressSFT UBM Cleared when the DSP56300 core writes to Universal Bus mode Fetch SFT =Reset, and Strq and Hstrhrrq are cleared Data path is lost when the reset state isHirq Dmae UBMDmae Haen Rreq UBM Receive Req uest EnableDmae Treq Rreq Hirq Pin Hdrq pinHreq Hint HF5 HF4 HF3 Host Interface Status Register HstrTrdy UBM UBM UBM UBM UBM UBM PCI PCI PCI PCI PCI PCIHost Request 23.Host Interface Status Register Hstr Bit DefinitionsHost interrupt a Treq Rreq HreqTransmitter Ready Host Receive Data RequestHost Transmit Data Request 15.Host Command Vector Register Hcvr Host Command Vector Register HcvrHost Command Vector 24.Host Command Vector Register Hcvr Bit DefinitionsBit Bit Name Reset Value Mode Description Number Hnmi UBMWhen the DSP56300 core acknowledges the host command Host CommandHost Master Receive Data Register Hrxm Host Slave Receive Data Register HrxsHost Transmit Data Register Htxr Universal Bus mode Dctrhm = $2 or $3 PCI Mode Dctrhm = $1Status/Command Configuration Register CSTR/CCMR Device ID/Vendor ID Configuration Register CDID/CVIDDPE SSE RMA RTA STA DPR FbbcSignaled System Error Detected Parity ErrorSignalled Target Abort Received Master AbortWait Cycle Control hardwired to zero System Error EnableParity Error Response Bus Master EnableClass Code/Revision ID Configuration Register CCCR/CRID HT7 HT6 HT5 HT4 HT3 HT2 HT1 HT0 Header Type hardwired to $00HT7-0 Read-only bits that identify the layout of bytes $10-$3FCcls Latency Timer HighCache Line Size Universal Bus Mode Base Address Memory Space Base Address Configuration Register CbmaPM8 PM7 PM6 PM5 PM4 MS1 MS0 MSI Memory Base Address High/LowMemory Base Address Low Hardwired to zeros 29. Memory Space Base Address Configuration Register CbmaPre-Fetch Hardwired to zero Memory Space Hardwired to zerosExample 6-5. Code for Setting the Csid IL5 IL4 Interrupt Line-Interrupt Pin Configuration RegisterCILPIL1 IL0 MaxlatHS PH PS HI32 Programming Model/Quick ReferenceDctr Hcie UBM HrspRble Dpcr MtieClrt Dpar DpmcDSR HCP HactDper Dpsr AperHdtc RdcqDmae TreqISA/EISA SFTHnmi HcvrHrxm HrxsCccr Ccmr RMAChty Cbma MSIRsma Rsmb Tsma Tclk STD GDB DDB RclkTsmb TX0 CRA SC0Essi Enhancements Serial Transmit Data Signal STD Essi Data and Control SignalsSerial Receive Data Signal SRD Serial Clock SCKSerial Control Signal SC1 Serial Control Signal SC0SYN TE0 TE1 TE2 SC0 SC1 SC2 SCK STD SRD Mode and Signal DefinitionsControl Bits Essi Signals Essi After Reset Serial Control Signal SC2Operation InitializationExceptions Operation Write data to all enabled transmit registers Operating Modes Normal, Network, and On-Demand Normal/Network/On-Demand Mode SelectionFrame Sync Selection Frame Sync Signal FormatSynchronous/Asynchronous Operating Modes Frame Sync Polarity Frame Sync Length for Multiple DevicesWord Length Frame Sync and Data Word Timing Flags Byte Format LSB/MSB for the TransmitterEssi Control Register a CRA Essi Programming ModelWL2 WL1 WL0 ALC PM7 PM6 PM5 PM4 PM3 PM2 PM1 PM0Select SC1 Essi Control Register a CRA Bit DefinitionsWord Length Control Essi Word Length SelectionFrame Rate Divider Control Alignment ControlPrescaler Range Prescale Modulus SelectCrbsyn = CRBTE1 CRBOF0 SSISRIF0Rclock TclockShfd Essi Control Register B CRBOF1 OF0 ESSI0 X$FFFFB6, ESSI1 X$FFFFA6Essi Control Register B CRB Bit Definitions Receive Enable Transmit Interrupt EnableTransmit 0 Enable TIETransmit 2 Enable Transmit 1 EnableMode Select Synchronous/AsynchronousFSL1 FSL0 OF1 Serial Control DirectionSerial Output Flag OF0TX Frame Sync TX Serial Data Serial Clock RX, TX Frame Sync RX, TX Serial DataSerial Clock RX Frame Sync RX Serial Data Essi Bit CRB SYN Bit OperationReceiver Interrupt or DMA Request and Flags Set Bit OperationSSI Control Register B CRB READ/WRITE Frame Sync FSL0 = 0, FSL1 = Data Flags Frame Sync FSL0 = 0, FSL1 = Data Out FlagsTransmitter Underrun Error Flag Receiver Overrun Error FlagEssi Status Register Ssisr Receive Data Register FullReceive Frame Sync Flag Essi Receive Shift RegisterTransmit Frame Sync Flag Serial Input FlagEssi Transmit Shift Registers Essi Receive Data Register RXTransmit Registers Receive RegistersWL0 Transmit Middle Byte Transmit Low Byte Register 24 BitLeast Significant MSBEssi Time Slot Register TSR Essi Transmit Data Registers TX2-0Transmit Slot Mask Registers TSMA, Tsmb TS9 TS8 TS7 TS6 TS5 TS4 TS3 TS2 TS1 TS015.ESSI Transmit Slot Mask Register B Tsmb RS7 RS6 Receive Slot Mask Registers RSMA, RsmbRS1 RS0 RS15 RS14 RS13 RS12 RS11 RS10Port Control Registers Pcrc and Pcrd Gpio Signals and RegistersESSI0/ESSI1 Essi Port Signal ConfigurationsPort Direction Registers Prrc and Prrd 20.Port Data Registers Pdrc X$FFFFBD Pdrd X $FFFFAD Port Data Registers Pdrc and PdrdSerial Communication Interface SCI Serial Communication Interface SCIMultidrop Mode Synchronous ModeAsynchronous Mode Wired-OR Mode I/O SignalsAddress Mode Wakeup Transmitting Data and Address CharactersSCI Serial Clock Sclk Receive Data RXDTransmit Data TXD SCI Registers After Reset SCI After ResetReie Sckp Stir Tmie TIE RIE Ilie Woms RWU Wake SBK SsftdSCI Initialization Preamble, Break, and Data Transmission Priority Exceptions Bootstrap Loading Through the SCI Boot Mode 2 or aSCI Programming Model WDS2 WDS1 WDS0 Bit Synchronous Data Shift Register ModeBit Asynchronous 1 Start, 8 Data, 1 Stop Bit Asynchronous 1 Start, 8 Data, 1 Even Parity, 1 StopSCI Data Word Formats Ssftd = 0 Stir Tmie TIE RIE Ilie Woms RWU Wake SBK Ssftd WDS2 SCI Control Register SCRReie SCI Transmit Interrupt Enable Timer Interrupt EnableSCI Receive Interrupt Enable Idle Line Interrupt EnableWoms Receiver EnableWired-OR Mode Select Wakeup Mode Select Receiver Wakeup EnableSend Break SCI Shift DirectionWDS1 WDS0 Mode Word FormatsWord Select Idle Rdrf Tdre Trne SCI Status Register SSRSCI Status Register SCI Status Register SSR Bit Definitions Transmitter Empty Idle Line FlagTdre TCM RCM SCP COD SCI Clock Control Register SccrTCM RCM SclkDivide by Bit CounterCD11-0 Sckp = 0 + Sckp =X1 Clock X16 Clock Sckp = RX, TX Data Ssftd =SCI Receive Data Shift Register SCI Data RegistersSCI Receive Register SRX SCI Transmit Register STX Sclk TXD RXD Port E Control Register PcrePE2 PE1 PE0 Port E Data Register Pdre Port E Direction Register PrrePRRE1 PRRE0 PDRE1 PDRE0Gpio Signals and Registers DSP56301 User’s Manual Triple Timer Module Triple Timer ModuleIndividual Timer Block Diagram Triple Timer Module Block DiagramGDB TpcrTimer Module Block Diagram Timer After ResetTimer Exceptions Timer InitializationTCSR0 Tcie Timer Gpio Mode Triple Timer ModesTC3 TC2 TC1 TC0 TIOTCR Tcpr Mode 0 internal clock, no timer output TRM =TLR Output Timer Pulse ModeMode 1 internal clock TRM = Pulse width = timer clock Period Mode 2 internal clock TRM = 1 first event Timer Toggle ModeToggle Timer = write preload = write compare Clock CLK/2 or prescale CLK= write compare Clock CLK/2 or prescale CLK Mode 2 internal clock TRM == write preload Mode 3 internal clock TRM = Timer Event Counter ModeInput External TIO Cpuclk += write compare Clock 10.Event Counter Mode, TRM =Measurement Input Width Mode Signal Measurement ModesInput Input width MeasurementMode 4 internal clock TRM = 1 first event Mode 4 internal clock TRM =Mode 5 internal clock TRM = Measurement Input Period ModeFirst event = write preload = write compare Input period Measurement InternalReads TCR period Counting, doesMay occur TOF=1 Mode 6 internal clock TRM = Measurement Capture ModeInterrupt Service reads TCR delay = M N clock periods InternalPulse width modulation Pulse Width Modulation PWM, ModePWM 16.Pulse Width Modulation Toggle Mode, TRM = Mode 7 internal clock TRM =17.Pulse Width Modulation Toggle Mode, TRM = Watchdog Modes Watchdog Pulse ModePulse Watchdog Output Internal= write preload First event Mode 9 internal clock TRM =Software does not reset watchdog timer watchdog times out Mode 10 internal clock TRM = Watchdog Toggle ModeWatchdog Output ToggleSpecial Cases Triple Timer Module Programming ModelDMA Trigger Prescaler CounterRegister Tplr Timer Prescaler Load23 22 21 20 19 18 17 Tplr = $FFFF83Prescaler Source Timer Prescaler Load Register TplrPS1 PS0 Prescaler Preload ValueTimer Control/Status Register Tcsr Timer Prescaler Count Register TpcrTCF TOF PCE TRM INVTimer Overflow Flag Timer Compare FlagPrescaler Clock Enable Data OutputInverter Timer Reload ModeDirection Number Function Timer ControlTimer Overflow Interrupt Enable Timer Compare Interrupt EnableTimer Enable TIO Programmed as Input TIO Programmed as Output Mode INV =Positive polarity Timer Load Register TLRPulse generated by Timer has Timer has negative Timer Count Register TCR Timer Compare Register TcprAppendix a DSP56301 User’s Manual HBS Can be stopped Hdben Aarv Mscte EQU LOOP0 Lbld Lble LOOP8 LOOP11 Rep Mac x0,x1,a x,lr0+ ORG PL,PL Patterns Write to Destination DSP56301 User’s Manual Programming Reference Chapter BTable B-1.Guide to Programming Sheets Bit Address Register Name Internal I/O Memory MapTable B-2. Internal I/O Memory Map X Data Memory Peripheral Bit Address Register Name Table B-2.Internal I/O Memory Map X Data Memory$FFCC $FFFFCC $FFCD $FFFFCD$FFCB $FFFFCB $FFCA $FFFFCA$FFBB $FFFFBB Essi $FFBC $FFFFBC$FFBA $FFFFBA $FFB9 $FFFFB9$FFAB $FFFFAB Essi $FFAC $FFFFAC$FFAA $FFFFAA $FFA9 $FFFFA9$FFFF91 $FFFF92$FFFF90 $FF8F $FFFF8FTable B-3. Interrupt Sources Interrupt Sources and PrioritiesVBA$6A Table B-3.Interrupt SourcesVBA$6C VBA$6ETable B-4.Interrupt Source Priorities Within an IPL Nonmaskable Host Command InterruptESSI0 receive last slot interrupt Figure B-1.Status Register SR Programming SheetsStop Delay External Bus DisableMemory Switch Mode Burst Mode EnableIrqc Mode Irqd ModeIrqb Mode Irqa ModeInterrupt Priority Register Iprp $FFFFFE Read/Write Triple Timer IPLHost IPL Crystal Range Bit Xtlr PLL Control Register Pctl $FFFFFD Read/WriteBus Control Register BCR $FFFFFB Read/Write Default Area Wait Control, BitsBus Request Hold, Bit Bus Lock Hold, BitDram Control Register DCR $FFFFFA Read/Write Bus Y Data Memory Enable, Bit Bus Packing Enable, BitBus X Data Memory Enable, Bit Bus Program Memory Enable, BitDMA Control Registers DCR5-DCR0 Reset = $000000 $FFFFE4, X$FFFFE8, X$FFFFEC Read/WriteApplication DSP Control Register Dctr Read/Write Address X FFFFC5DSP PCI Control Register Dpcr Address XFFFFC6 Read/Write = Enables master receive interruptsFigure B-12.DSP PCI Master Control Register Dpmc Figure B-13.DSP PCI Address Register Dpar PCI Bus Command, BitsHI32 Control Register Hctr Read/Write Host Non-Maskable Interrupt, Bit HI32 Command Vector Register Hcvr Read/WriteSignaled System Error, Bit Detected Parity Error, BitSignalled Target Abort, Bit System Error Enable, BitRead/Write Latency Timer High, BitsHeader Type, Bits Cache Line Size, BitsReset = $00000000 HI32 Memory Space Base Address Configuration Register CbmaPCI Mode Base Address High, Bits Pre-fetch, Bit Memory Space Indicator, BitSubsystem ID Register, Bits 31-16 Specifies the subsystem ID ESSI1-X$FFFFA5 Read/Write Essi Control Register a CRAx ESSI0-X$FFFFB5 Read/WriteESSI1-X$FFFFA6 Read/Write Essi Control Register B CRBxESSI0-X$FFFFB6 Read/Write ESSI1-X$FFFFA4 Read/Write Essi Transmit Slot Mask a TSMA0-1 ESSI0-X$FFFFB4 Read/WriteEssi Transmit Slot Mask B TSMB0-1 ESSI0-X$FFFFB3 Read/Write ESSI1-X$FFFFA3 Read/WriteSCI Control Register SCR $FFFF9C Read/Write Clock Out Divider SCI Clock Control Register Sccr Address X$FFFF9B Read/WriteReceiver Clock Mode/Source Timer Prescaler Load Register Tplr $FFFF83 Read/Write Figure B-25.Timer Prescaler Load Register TplrTCSR1$FFFF8B Read/Write TCSR2$FFFF87 Read/Write Timer Control/Status Register TCSR0$FFFF8F Read/WriteTLR1-X$FFFF8A Write Only TLR2-X$FFFF86 Write Only Timer Load Register TLR0-2 TLR0-X$FFFF8E Write OnlyHost Data Register HDR $FFFFC9 Write Port B HI08Host Data Direction Register Hddr X$FFFFC8 Write Port C Control Register Pcrc $FFFFBF Read/Write Port C ESSI0Port C Direction Register Prrc $FFFFBE Read/Write Port C Gpio Data Register Pdrc $FFFFBD Read/WritePort D Control Register Pcrd $FFFFAF Read/Write Port D ESSI1Port D Direction Register Prrd $FFFFAE Read/Write Port D Gpio Data Register Pdrd $FFFFAD Read/WritePort E Control Register Pcre $FFFF9F Read/Write Port E SCIPort E Direction Register Prre $FFFF9E Read/Write Port E Gpio Data Register Pdre $FFFF9D Read/WriteProgramming Sheets DSP56301 User’s Manual Index Index-2 DSP56301 User’s Manual Index-3 Index-4 DSP56301 User’s Manual Index-5 Index-6 DSP56301 User’s Manual Index-7 Index-8 DSP56301 User’s Manual Index-9 Index-10 DSP56301 User’s Manual Index-11 Index-12 DSP56301 User’s Manual Index-13 Index-14 DSP56301 User’s Manual Index-15 Index-16 DSP56301 User’s Manual