Clear Transmitter

HI32 DSP-Side Programming Model

Table 6-11.DSP PCI Control Register (DPCR) Bit Definitions (Continued)

Bit Number	Bit Name	Reset Value	Description

14	CLRT	0	Clear Transmitter
			Clears the HI32 master-to-host bus data path in PCI mode (DCTR[HM]
			= $1). When the DSP56300 core sets CLRT, the HI32 hardware clears
			the master DSP-to-host bus data path (that is, the DTXM-HRXM FIFO
			is forced empty), thus setting the PCI Master Transmit Data Request bit
			(MTRQ) in the DPSR. Then it clears CLRT. The DSP56300 core cannot
			write a value of zero to CLRT. To assure operation, the DSP56300 core
			can set CLRT only under the following conditions:
			1. MARQ is set in the DPSR (that is, the DSP56300 core has not
			initiated a PCI transaction).
			2. No DSP56300 core DMA channel is enabled to service HI32
			master transmit data DMA requests.
			CLRT is ignored when the HI32 is not in PCI mode (DCTR[HM]≠$1).

13		0	Reserved. Write to 0 for future compatibility.

12	TCIE	0	Transfer Complete Interrupt Enable
			Enables/disables a DSP56300 core interrupt request in PCI mode
			(DCTR[HM] = $1). The request is generated if the host data transfer
			complete (HDTC) status bit in the DSP PCI Status Register (DPSR) is
			set. When TCIE is cleared, transfer complete interrupt requests are
			disabled.

11–10		0	Reserved. Write to 0 for future compatibility.

9	TTIE	0	Transaction Termination Interrupt Enable
			Enables/disables a DSP56300 core interrupt request in PCI mode
			(DCTR[HM] = $1) when the HI32, as a PCI master, executes a time-out
			termination (TO is set), a target-initiated disconnect (DPSR[TDIS] is
			set), or a retry termination (TRTY is set). When TTIE is cleared,
			transaction termination interrupt requests are disabled.

8		0	Reserved. Write to 0 for future compatibility.

7	TAIE	0	Transaction Abort Interrupt Enable
			Enables/disables a DSP56300 core interrupt request in PCI mode
			(DCTR[HM] = $1) when the HI32, as a PCI master, executes a
			master-abort termination (DPSR[MAB] is set) or a target initiated
			target-abort termination (TAB is set). If TAIE is cleared, transaction
			abort interrupt requests are disabled.

6		0	Reserved. Write to 0 for future compatibility.

5	PEIE	0	Parity Error Interrupt Enable
			Enables/disables a DSP56300 core interrupt request when a parity
			error is detected in PCI mode (DCTR[HM] = $1). When PEIE is cleared,
			parity error interrupt requests are disabled. When PEIE is set, a parity
			error interrupt request is generated if a parity error (address or data) is
			detected and the address parity error (APER) status bit or the data
			parity error (DPER) status bit in the DPSR is set.

Host Interface (HI32)

6-29

DSP56301 specifications

The Motorola DSP56301 is a highly efficient digital signal processor, specifically engineered for real-time audio and speech processing applications. This DSP is part of Motorola's renowned DSP56300 family, which is recognized for its innovative features and outstanding performance in the realm of digital signal processing.

One of the main features of the DSP56301 is its ability to handle complex computations at high speeds. With a maximum clock frequency of 66 MHz, it delivers fast performance, enabling it to process audio signals in real time. The chip is built on a 24-bit architecture, which allows for high-resolution audio processing. This is particularly beneficial in applications such as telecommunications, consumer audio devices, and professional audio equipment, where precision is paramount.

The DSP56301 boasts a comprehensive instruction set that includes efficient mathematical operations, which are essential for digital filters and audio effects processing. One of the key innovations of this device is its dual data path architecture, which permits simultaneous processing of multiple data streams. This feature significantly enhances the device's throughput and responsiveness, making it suitable for demanding applications such as voice recognition and synthesis.

In terms of memory regions, the DSP56301 includes several on-chip memory categories, such as program memory, data memory, and a specialized memory for coefficients. The architecture's support for external memory expansion further increases its versatility, allowing designers to tailor systems to their specific requirements.

The DSP56301 implements advanced features such as a powerful on-chip hardware multiplier and accumulator, simplifying complex mathematical tasks and accelerating the execution of algorithms. Its flexible interrupt system enhances its capability to respond to time-sensitive operations, while the integrated serial ports facilitate efficient data communication with external devices.

Power consumption is also a vital characteristic of the DSP56301. It is designed with energy efficiency in mind, allowing for extended operation in battery-powered devices. The chip’s low power requirements are particularly advantageous in portable audio devices and other applications where energy conservation is crucial.

In conclusion, the Motorola DSP56301 is an exceptional digital signal processor that combines high processing power, flexibility, and efficiency. Its main features, advanced technologies, and robust architecture make it a top choice for developers seeking to create sophisticated audio and signal processing systems. With its enduring legacy in the industry, the DSP56301 continues to be relevant in a variety of modern applications, ensuring it remains a valuable tool for engineers and designers.

Motorola DSP56301 user manual Clear Transmitter, Transfer Complete Interrupt Enable

Models: DSP56301

Table 6-11.DSP PCI Control Register (DPCR) Bit Definitions (Continued)

Transfer Complete Interrupt Enable

Transaction Termination Interrupt Enable

Transaction Abort Interrupt Enable

Parity Error Interrupt Enable

Host Interface (HI32)

DSP56301 specifications