Index-12 DSP56301 User’s Manual

Receive Slot Mask Registers (RSMA and RSMB) 7-14,7-35

Receive with Exception Interrupt Enable (REIE) bit 8-12Received Bit 8 (R8) bit 8-17

Received Master Abort (RMA) bit 6-65Received Target Abort (RTA) 6-65Receiver Enable (RE) bit 8-14Receiver Overrun Error Flag (ROE) 7-28Receiver Wakeup Enable (RWU) bit 8-15Related Documents and Web Sites 1-14Remaining Data Count (RDC[5–0]) bits 6-38Remaining Data Count Qualifier (RDCQ) bit 6-38RESET 2-9

reset

STOP 6-12reset state 4-2,4-5HI32 6-12

reverse-carry adder 1-7

Revision ID (RID[7–0]) bits 6-67ROM, bootstrap 3-1,3-3Rounding Mode (RM) bit 4-7RX clock 7-11

SC register 1-8Scaling (S) bit 4-10Scaling (S) Mode bits 4-10

SCI Clock Control Register (SCCR) 8-9,8-19bit definitions 8-19

Clock Divider (CD) 8-20Clock Out Divider (COD) 8-19Clock Prescaler (SCP) 8-19programming sheet B-36

Receive Clock Mode Source (RCM) 8-19Transmit Clock Source (TCM) 8-19

SCI Clock Polarity (SCKP) bit 8-12SCI Control Register (SCR) 8-9,8-12

bit definitions 8-12

Idle Line Interrupt Enable (ILIE) 8-13programming sheet B-35

Receive with Exception Interrupt Enable (REIE) 8-12Receiver Enable (RE) 8-14

Receiver Wakeup Enable (RWU) 8-15SCI Clock Polarity (SCKP) 8-12

SCI Receive Interrupt Enable (RIE) 8-13SCI Shift Direction (SSFTD) 8-15

SCI Transmit Interrupt Enable (TIE) 8-13Send Break (SBK) 8-15

Timer Interrupt Enable (TMIE) 8-13Timer Interrupt Rate (STIR) 8-12Transmitter Enable (TE) 8-14Wakeup Mode Select (WAKE) 8-15Wired-OR Mode Select (WOMS) 8-14

Word Select (WDS) 8-16

SCI Interrupt Priority Level (SCL) bits 4-16SCI Receive Data Register (SRX) 8-9,8-22SCI Receive Interrupt Enable (RIE) bit 8-13SCI Serial Clock signal (SCLK) 8-4

SCI Shift Direction (SSFTD) 8-15

SCI Status Register (SSR) 8-9,8-17bit definitions 8-17

Framing Error Flag (FE) 8-17Idle Line Flag (IDLE) 8-18Overrun Error Flag (OR) 8-18Parity Error (PE) 8-17

Receive Data Register Full (RDRF) 8-18Received Bit 8 (R8) 8-17

Transmit Data Register Empty (TDRE) 8-18Transmitter Empty (TRNE) 8-18

SCI Transmit Data Address Register (STXA) 8-9SCI Transmit Data Register (STX or STXA) 8-22SCI Transmit Data Register (STX) 8-9,8-23SCI Transmit Interrupt Enable (TIE) bit 8-13SCLK 8-2,8-6

SCS byte 4-12

Select SCK (SSC1) bit 7-15Self-Configuration mode 6-12,6-44,6-72Send Break (SBK) bit 8-15

Serial Clock (SCK) 7-3Serial Clock (SCLK), SCI 8-2

Serial Communications Interface (SCI) 1-5,1-6,1-13,2-2,8-1

Address Mode Wakeup 8-3Asynchronous mode 8-2bootstrap loading 8-8crystal frequency 8-6data registers 8-22

Data Word Formats 8-10enable wakeup function 8-15enable/disable SCI receive data with exception

interrupt 8-12exceptions 8-8

Idle Line 8-9Receive Data 8-8

Receive Data with Exception Status 8-8Timer 8-9

Transmit Data 8-8GPIO 5-6

GPIO functionality 8-24I/O signals 8-3

Idle Line Wakeup mode 8-3individual reset state (PCR = $0) 8-6initialization 8-6

Inter-processor messages 8-2interrupts 8-6

Multidrop mode 8-2operating mode 8-1

Index-12

DSP56301 User’s Manual

DSP56301 specifications

The Motorola DSP56301 is a highly efficient digital signal processor, specifically engineered for real-time audio and speech processing applications. This DSP is part of Motorola's renowned DSP56300 family, which is recognized for its innovative features and outstanding performance in the realm of digital signal processing.

One of the main features of the DSP56301 is its ability to handle complex computations at high speeds. With a maximum clock frequency of 66 MHz, it delivers fast performance, enabling it to process audio signals in real time. The chip is built on a 24-bit architecture, which allows for high-resolution audio processing. This is particularly beneficial in applications such as telecommunications, consumer audio devices, and professional audio equipment, where precision is paramount.

The DSP56301 boasts a comprehensive instruction set that includes efficient mathematical operations, which are essential for digital filters and audio effects processing. One of the key innovations of this device is its dual data path architecture, which permits simultaneous processing of multiple data streams. This feature significantly enhances the device's throughput and responsiveness, making it suitable for demanding applications such as voice recognition and synthesis.

In terms of memory regions, the DSP56301 includes several on-chip memory categories, such as program memory, data memory, and a specialized memory for coefficients. The architecture's support for external memory expansion further increases its versatility, allowing designers to tailor systems to their specific requirements.

The DSP56301 implements advanced features such as a powerful on-chip hardware multiplier and accumulator, simplifying complex mathematical tasks and accelerating the execution of algorithms. Its flexible interrupt system enhances its capability to respond to time-sensitive operations, while the integrated serial ports facilitate efficient data communication with external devices.

Power consumption is also a vital characteristic of the DSP56301. It is designed with energy efficiency in mind, allowing for extended operation in battery-powered devices. The chip’s low power requirements are particularly advantageous in portable audio devices and other applications where energy conservation is crucial.

In conclusion, the Motorola DSP56301 is an exceptional digital signal processor that combines high processing power, flexibility, and efficiency. Its main features, advanced technologies, and robust architecture make it a top choice for developers seeking to create sophisticated audio and signal processing systems. With its enduring legacy in the industry, the DSP56301 continues to be relevant in a variety of modern applications, ensuring it remains a valuable tool for engineers and designers.

Motorola user manual Index-12 DSP56301 User’s Manual

Models: DSP56301

Index-12

DSP56301 User’s Manual

DSP56301 specifications