Motorola DSP56301 user manual HI32 Features, Core-Side and Host-Side

Models: DSP56301

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Features

Table 6-1.HI32 Features, Core-Side and Host-Side

Feature

Core-Side Interface

Host-Side Interface

 

 

 

 

 

 

Mapping

11 internal I/O space locations

PCI mode: Memory space:16 K Dword (32-bit

 

 

wide) locations composed of:

 

 

ν Three 32-bit read/write registers

 

 

(control, status, and host command)

 

 

ν 16377 32-bit read/write locations

 

 

corresponding to one 32-bit input data

 

 

FIFO and one 32-bit output data FIFO

 

 

ν Four 32-bit reserved locations (read only)

 

 

ν Configuration space:Sixty-four 32-bit

 

 

locations (57 of which are reserved)

 

 

Universal Bus mode:

 

 

ν Three 24-bit read/write registers

 

 

(control, status and host command)

 

 

ν One 24-bit read/write register for input

 

 

and output data FIFO (four of which are

 

 

reserved)

 

 

ν Eight locations up to 24-bits wide (four are

 

 

reserved)

 

 

 

Word Size

24 bits

8, 16, 24, or 32 bits

 

 

 

PCI Mode: Data

Output data alignment of 16 bit words to 16-bit

 

Format

double words (Dwords)

 

Conversion

 

 

 

Output data alignment of 24-bit words to 32-bit

 

 

Dwords

 

 

ν Left aligned and zero filled

 

 

ν Right aligned and zero extended

 

 

ν Right aligned and sign extended

 

 

Input data alignment of 32-bit Dwords to 24-bit

 

 

words (three MSBs, three LSBs)

 

 

True 32-bit input and output data transfers

 

 

32-bit PCI bus data to two DSP56300 core 16-bit

 

 

words, and vice versa

 

 

 

 

Universal Bus

Output data alignment of 24-bit words to 16-bit

 

Mode: Data

words (two MSBs, two LSBs)

 

Format

 

 

Conversion

Input data alignment of 16-bit words to 24-bit

 

 

words

 

 

ν left aligned and zero filled

 

 

ν right aligned and zero extended

 

 

ν right aligned and sign extended

 

 

 

 

Data Buffers

FIFOs up to eight words deep on both transmit

FIFOs six or eight words deep on transmit and

 

and receive data paths

receive data paths, five deep in Universal Bus

 

 

mode

 

 

 

6-2

DSP56301 User’s Manual

Page 120
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Motorola DSP56301 user manual HI32 Features, Core-Side and Host-Side

DSP56301 specifications

The Motorola DSP56301 is a highly efficient digital signal processor, specifically engineered for real-time audio and speech processing applications. This DSP is part of Motorola's renowned DSP56300 family, which is recognized for its innovative features and outstanding performance in the realm of digital signal processing.

One of the main features of the DSP56301 is its ability to handle complex computations at high speeds. With a maximum clock frequency of 66 MHz, it delivers fast performance, enabling it to process audio signals in real time. The chip is built on a 24-bit architecture, which allows for high-resolution audio processing. This is particularly beneficial in applications such as telecommunications, consumer audio devices, and professional audio equipment, where precision is paramount.

The DSP56301 boasts a comprehensive instruction set that includes efficient mathematical operations, which are essential for digital filters and audio effects processing. One of the key innovations of this device is its dual data path architecture, which permits simultaneous processing of multiple data streams. This feature significantly enhances the device's throughput and responsiveness, making it suitable for demanding applications such as voice recognition and synthesis.

In terms of memory regions, the DSP56301 includes several on-chip memory categories, such as program memory, data memory, and a specialized memory for coefficients. The architecture's support for external memory expansion further increases its versatility, allowing designers to tailor systems to their specific requirements.

The DSP56301 implements advanced features such as a powerful on-chip hardware multiplier and accumulator, simplifying complex mathematical tasks and accelerating the execution of algorithms. Its flexible interrupt system enhances its capability to respond to time-sensitive operations, while the integrated serial ports facilitate efficient data communication with external devices.

Power consumption is also a vital characteristic of the DSP56301. It is designed with energy efficiency in mind, allowing for extended operation in battery-powered devices. The chip’s low power requirements are particularly advantageous in portable audio devices and other applications where energy conservation is crucial.

In conclusion, the Motorola DSP56301 is an exceptional digital signal processor that combines high processing power, flexibility, and efficiency. Its main features, advanced technologies, and robust architecture make it a top choice for developers seeking to create sophisticated audio and signal processing systems. With its enduring legacy in the industry, the DSP56301 continues to be relevant in a variety of modern applications, ensuring it remains a valuable tool for engineers and designers.