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Motorola DSP56301 Essi Receive Shift Register, Receive Frame Sync Flag, Transmit Frame Sync Flag

Models: DSP56301

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ESSI Programming Model

Table 7-5.ESSI Status Register (SSISR) Bit Definitions (Continued)

Bit Number

Bit Name

Reset Value

 

Description

 

 

 

 

 

 

 

 

3

RFS

0

Receive Frame Sync Flag

 

 

 

When set, the RFS bit indicates that a receive frame sync occurred during

 

 

 

the reception of a word in the serial receive data register. In other words,

 

 

 

the data word is from the first time slot in the frame. When the RFS bit is

 

 

 

cleared and a word is received, it indicates (only in Network mode) that the

 

 

 

frame sync did not occur during reception of that word. RFS is valid only if

 

 

 

the receiver is enabled (that is, if the RE bit is set).

 

 

 

Note:

In Normal mode, RFS is always read as 1 when data is read

 

 

 

 

because there is only one time slot per frame, the frame sync

 

 

 

 

time slot.

 

 

 

 

2

TFS

0

Transmit Frame Sync Flag

 

 

 

When set, TFS indicates that a transmit frame sync occurred in the current

 

 

 

time slot. TFS is set at the start of the first time slot in the frame and

 

 

 

cleared during all other time slots. If the transmitter is enabled, data

 

 

 

written to a transmit data register during the time slot when TFS is set is

 

 

 

transmitted (in Network mode) during the second time slot in the frame.

 

 

 

TFS is useful in Network mode to identify the start of a frame. TFS is valid

 

 

 

only if at least one transmitter is enabled that is, when TE0, TE1, or TE2 is

 

 

 

set).

 

 

 

 

Note:

In Normal mode, TFS is always read as 1 when data is being

 

 

 

 

transmitted because there is only one time slot per frame, the

 

 

 

 

frame sync time slot.

 

 

 

 

1

IF1

0

Serial Input Flag 1

 

 

 

The ESSI latches any data on the SC1 signal during reception of the first

 

 

 

received bit after the frame sync is detected. IF1 is updated with this data

 

 

 

when the data in the receive shift register transfers into the receive data

 

 

 

register. IF1 is enabled only when SC1 is an input flag and Synchronous

 

 

 

mode is selected; that is, when SC1 is programmed as ESSI in the port

 

 

 

control register (PCR), the SYN bit is set, and the TE2 and SCD1 bits are

 

 

 

cleared. If it is not enabled, IF1 is cleared.

 

 

 

 

0

IF0

0

Serial Input Flag 0

 

 

 

The ESSI latches any data on the SC0 signal during reception of the first

 

 

 

received bit after the frame sync is detected. The IF0 bit is updated with

 

 

 

this data when the data in the receive shift register transfers into the

 

 

 

receive data register. IF0 is enabled only when SC0 is an input flag and

 

 

 

the Synchronous mode is selected; that is, when SC0 is programmed as

 

 

 

ESSI in the port control register (PCR), the SYN bit is set, and the TE1

 

 

 

and SCD0 bits are cleared. If it is not enabled, the IF0 bit is cleared.

 

 

 

 

 

7.5.4ESSI Receive Shift Register

The 24-bit Receive Shift Register (see Figure 7-12and Figure 7-13) receives incoming data from the serial receive data signal. The selected (internal/external) bit clock shifts data in when the associated frame sync I/O is asserted. Data is received MSB first if SHFD is cleared and LSB first if SHFD is set. Data transfers to the ESSI Receive Data Register (RX) after 8, 12, 16, 24, or 32 serial clock cycles are counted, depending on the word length control bits in the CRA.

Enhanced Synchronous Serial Interface (ESSI)

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Motorola DSP56301 Essi Receive Shift Register, Receive Frame Sync Flag, Transmit Frame Sync Flag, Serial Input Flag
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DSP56301 specifications

The Motorola DSP56301 is a highly efficient digital signal processor, specifically engineered for real-time audio and speech processing applications. This DSP is part of Motorola's renowned DSP56300 family, which is recognized for its innovative features and outstanding performance in the realm of digital signal processing.

One of the main features of the DSP56301 is its ability to handle complex computations at high speeds. With a maximum clock frequency of 66 MHz, it delivers fast performance, enabling it to process audio signals in real time. The chip is built on a 24-bit architecture, which allows for high-resolution audio processing. This is particularly beneficial in applications such as telecommunications, consumer audio devices, and professional audio equipment, where precision is paramount.

The DSP56301 boasts a comprehensive instruction set that includes efficient mathematical operations, which are essential for digital filters and audio effects processing. One of the key innovations of this device is its dual data path architecture, which permits simultaneous processing of multiple data streams. This feature significantly enhances the device's throughput and responsiveness, making it suitable for demanding applications such as voice recognition and synthesis.

In terms of memory regions, the DSP56301 includes several on-chip memory categories, such as program memory, data memory, and a specialized memory for coefficients. The architecture's support for external memory expansion further increases its versatility, allowing designers to tailor systems to their specific requirements.

The DSP56301 implements advanced features such as a powerful on-chip hardware multiplier and accumulator, simplifying complex mathematical tasks and accelerating the execution of algorithms. Its flexible interrupt system enhances its capability to respond to time-sensitive operations, while the integrated serial ports facilitate efficient data communication with external devices.

Power consumption is also a vital characteristic of the DSP56301. It is designed with energy efficiency in mind, allowing for extended operation in battery-powered devices. The chip’s low power requirements are particularly advantageous in portable audio devices and other applications where energy conservation is crucial.

In conclusion, the Motorola DSP56301 is an exceptional digital signal processor that combines high processing power, flexibility, and efficiency. Its main features, advanced technologies, and robust architecture make it a top choice for developers seeking to create sophisticated audio and signal processing systems. With its enduring legacy in the industry, the DSP56301 continues to be relevant in a variety of modern applications, ensuring it remains a valuable tool for engineers and designers.