Manuals / Motorola / Home Audio / Stereo System

Motorola DSP56301 user manual Host-Side Registers PCI Memory Address Space

Models: DSP56301

1 372
Download 372 pages 304 b
Page 165
Image 165

 

 

 

 

 

 

 

Host-Side Programming Model

 

 

 

 

 

 

 

 

 

 

 

 

 

Table 6-19.Host-Side Registers (PCI Memory Address Space1)

 

 

Base Address: $0000

Reserved

 

 

 

(4 Dwords)

 

 

 

 

 

 

 

 

 

 

 

 

 

Base Address:$000C

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Base Address: $0010

HI32 Control Register (HCTR)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Base Address: $0014

HI32 Status Register (HSTR)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Base Address: $0018

Host Command Vector Register (HCVR)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Base Address:$001C

 

 

 

 

 

 

 

 

 

 

 

Host Transmit/Slave Receive Data Register (HTXR/HRXS)

(16377 Dwords)

 

 

 

 

Base Address:$FFFC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Note:

Addresses are shown in bytes.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Table 6-20.Host-Side Registers (PCI Configuration Address Space1)

 

 

$00 CDID/CVID

Device ID (CDID)

 

 

Vendor ID (CVID)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

$04 CSTR/CCMR

Status (CSTR)

 

 

Command (CCMR)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

$08 CCCR/CRID

Class Code (CCCR)

 

 

 

Revision ID (CRID)

 

 

 

 

 

 

 

 

 

 

 

 

$0C CHTY/CLAT

 

Header Type

 

Latency Timer

Cache Line (CCLS)

 

 

 

 

 

 

 

(CHTY)

 

(CLAT)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

$10 CBMA

Memory Space Base Address (CBMA)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

$14

 

Reserved(6 Dwords)

 

 

 

 

 

 

 

$28

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

$2C

CSID

Subsystem ID and Subsystem Vendor ID (CSID)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

$30

 

Reserved

 

 

 

(3 Dwords)

 

 

 

$38

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

$3C (CILP)

MAX_LAT

MIN_GNT

 

Interrupt Line

Interrupt Pin

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

$40

 

 

 

 

 

(48 Dwords)

 

 

 

 

$FC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Note:

Addresses are shown in bytes.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Table 6-21.Host-Side Registers (Universal Bus Mode Address Space1)

 

 

Base Address: $0

 

Reserved

 

(4 Locations)

 

 

 

 

Base Address: $3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Base Address: $4

 

HI32 Control Register (HCTR)

 

 

 

 

 

 

 

 

 

 

 

 

 

Base Address: $5

 

HI32 Status Register (HSTR)

 

 

 

 

 

 

 

 

 

 

 

 

 

Base Address: $6

 

Host Command Vector Register (HCVR)

 

 

 

 

 

 

 

 

 

 

 

Base Address: $7

 

Host Transmit/Slave Receive Data FIFO (HTXR/HRXS)

 

 

 

 

 

 

 

 

 

 

 

Note:

Addresses shown are in words (locations). The base address is defined by eight bits of the CBMA register.

 

 

 

 

 

 

 

 

 

 

 

 

Host Interface (HI32)

6-47

Page 164 Page 166
Page 165
Image 165
Motorola DSP56301 Host-Side Registers PCI Memory Address Space, Host-Side Registers PCI Configuration Address Space
Page 164 Page 166

DSP56301 specifications

The Motorola DSP56301 is a highly efficient digital signal processor, specifically engineered for real-time audio and speech processing applications. This DSP is part of Motorola's renowned DSP56300 family, which is recognized for its innovative features and outstanding performance in the realm of digital signal processing.

One of the main features of the DSP56301 is its ability to handle complex computations at high speeds. With a maximum clock frequency of 66 MHz, it delivers fast performance, enabling it to process audio signals in real time. The chip is built on a 24-bit architecture, which allows for high-resolution audio processing. This is particularly beneficial in applications such as telecommunications, consumer audio devices, and professional audio equipment, where precision is paramount.

The DSP56301 boasts a comprehensive instruction set that includes efficient mathematical operations, which are essential for digital filters and audio effects processing. One of the key innovations of this device is its dual data path architecture, which permits simultaneous processing of multiple data streams. This feature significantly enhances the device's throughput and responsiveness, making it suitable for demanding applications such as voice recognition and synthesis.

In terms of memory regions, the DSP56301 includes several on-chip memory categories, such as program memory, data memory, and a specialized memory for coefficients. The architecture's support for external memory expansion further increases its versatility, allowing designers to tailor systems to their specific requirements.

The DSP56301 implements advanced features such as a powerful on-chip hardware multiplier and accumulator, simplifying complex mathematical tasks and accelerating the execution of algorithms. Its flexible interrupt system enhances its capability to respond to time-sensitive operations, while the integrated serial ports facilitate efficient data communication with external devices.

Power consumption is also a vital characteristic of the DSP56301. It is designed with energy efficiency in mind, allowing for extended operation in battery-powered devices. The chip’s low power requirements are particularly advantageous in portable audio devices and other applications where energy conservation is crucial.

In conclusion, the Motorola DSP56301 is an exceptional digital signal processor that combines high processing power, flexibility, and efficiency. Its main features, advanced technologies, and robust architecture make it a top choice for developers seeking to create sophisticated audio and signal processing systems. With its enduring legacy in the industry, the DSP56301 continues to be relevant in a variety of modern applications, ensuring it remains a valuable tool for engineers and designers.