Rreq UBM, Receive Req uest Enable | Motorola DSP56301 specs

Host-Side Programming Model

Table 6-22.Host Interface Control Register (HCTR) Bit Definitions (Continued)

Bit	Bit Name	Reset	Mode	Description
Number	Bit Name	Value	Mode	Description
Number		Value


2	RREQ	0	UBM	Receive Request Enable
				Controls the HIRQ and HDRQ pins for DSP-to-host data transfers in a
				Universal Bus mode (DCTR[HM] = $2 or $3). When DMAE is cleared,
				RREQ enables the host interrupt request (HIRQ) pin if the host receive
				data request (HRRQ) status bit in the HSTR is set. If RREQ is cleared,
				HRRQ host interrupt requests are disabled. The host interrupt request
				HIRQ pin is asserted if HRRQ is set. HDRQ is deasserted.
				If DMAE is set, RREQ enables the host DMA request (HDRQ) pin when
				the host receive data request (HRRQ) status bit in the HSTR is set. If
				RREQ is cleared, HRRQ host DMA requests are disabled. If RREQ is set,
				the host DMA request HDRQ pin is asserted if HRRQ is set. HIRQ is
				deasserted (high impedance) if HIRD = 0 in the DCTR.

Note: In a Universal Bus mode (DCTR[HM] = $2 or $3), when both the TREQ and RREQ control bits (in the HCTR) are cleared, host interrupt request / strobe / acknowledge hardware handshake (using the HIRQ / Data Strobe / HTA pins) is disabled. The host can poll the HTRQ, and HSTR[HRRQ] status bits or use the host data strobe/acknowledge hardware handshake (using the Data Strobe / HTA pins).


DMAE	TREQ	RREQ		HIRQ Pin	HDRQ pin

0	0	0	deasserted 2 (HRRQ,		high impedance
			HTRQ polling)

0	1	0	HTRQ Host Interrupt		high impedance
			Request Enabled

0	1	1	HRRQ, HTRQ Interrupt		high impedance
			Requests Enabled

1	0	0	deasserted1		high impedance

1	0	1	deasserted1		HRRQ DMA Request
					Enabled

1	1	0	deasserted1		HTRQ DMA Request
					Enabled

1	1	1	deasserted1		HRRQ, HTRQ Host DMA
					Requests Enabled

Host Interface (HI32)

6-55

DSP56301 specifications

The Motorola DSP56301 is a highly efficient digital signal processor, specifically engineered for real-time audio and speech processing applications. This DSP is part of Motorola's renowned DSP56300 family, which is recognized for its innovative features and outstanding performance in the realm of digital signal processing.

One of the main features of the DSP56301 is its ability to handle complex computations at high speeds. With a maximum clock frequency of 66 MHz, it delivers fast performance, enabling it to process audio signals in real time. The chip is built on a 24-bit architecture, which allows for high-resolution audio processing. This is particularly beneficial in applications such as telecommunications, consumer audio devices, and professional audio equipment, where precision is paramount.

The DSP56301 boasts a comprehensive instruction set that includes efficient mathematical operations, which are essential for digital filters and audio effects processing. One of the key innovations of this device is its dual data path architecture, which permits simultaneous processing of multiple data streams. This feature significantly enhances the device's throughput and responsiveness, making it suitable for demanding applications such as voice recognition and synthesis.

In terms of memory regions, the DSP56301 includes several on-chip memory categories, such as program memory, data memory, and a specialized memory for coefficients. The architecture's support for external memory expansion further increases its versatility, allowing designers to tailor systems to their specific requirements.

The DSP56301 implements advanced features such as a powerful on-chip hardware multiplier and accumulator, simplifying complex mathematical tasks and accelerating the execution of algorithms. Its flexible interrupt system enhances its capability to respond to time-sensitive operations, while the integrated serial ports facilitate efficient data communication with external devices.

Power consumption is also a vital characteristic of the DSP56301. It is designed with energy efficiency in mind, allowing for extended operation in battery-powered devices. The chip’s low power requirements are particularly advantageous in portable audio devices and other applications where energy conservation is crucial.

In conclusion, the Motorola DSP56301 is an exceptional digital signal processor that combines high processing power, flexibility, and efficiency. Its main features, advanced technologies, and robust architecture make it a top choice for developers seeking to create sophisticated audio and signal processing systems. With its enduring legacy in the industry, the DSP56301 continues to be relevant in a variety of modern applications, ensuring it remains a valuable tool for engineers and designers.

Motorola DSP56301 user manual Rreq UBM, Receive Req uest Enable, Dmae Treq Rreq, Hirq Pin Hdrq pin

Models: DSP56301

Host-Side Programming Model

Table 6-22.Host Interface Control Register (HCTR) Bit Definitions (Continued)

Bit

Mode

RREQ

UBM

Receive Request Enable

DMAE

TREQ

RREQ

HIRQ Pin

HDRQ pin

Host Interface (HI32)

DSP56301 specifications